Acer Aspire 5334 Service Guide - Page 148

Code 0x28 0x29 0x30 0x31 0x32 0x33 0x34 0x35 0xAF Description Enable all clocks on populated rows Perform JEDEC memory initialization for all memory rows Perform steps required after memory init Program DRAM throttling and throttling event registers Setup DRAM control register for normal operation and enable Enable RCOMP Clear DRAM initialization bit in the SB Initialization Sequence Completed, program graphic clocks Disable access to the XMM registers 138 Chapter 4