Acer Aspire 5515 Acer Aspire 5515 Notebook Service Guide - Page 146

Post Codes These tables describe the POST codes and descriptions during the POST. Chipset POST Codes The following table details the chipset POST codes and functions used in the POST. Code 02h 03h 04h 06h 08h 09h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 16h 17h 18h 1Ah 1Ch 20h 22h 24h 26h 28h 29h 2Ah 2Ch 2Eh 2Fh 30h 32h 33h 36h 38h 3Ah Beeps 1-2-2-3 8254 8237 1-3-1-1 1-3-1-3 1-3-4-1 1-3-4-3 1-4-1-1 POST Routine Description Verify Real Mode Disable Non-Maskable Interrupt (NMI) Get CPU type Initialize system hardware Initialize chipset with initial POST values Set IN POST flag Initialize CPU registers Enable CPU cache Initialize caches to initial POST values Initialize I/O component Initialize the local bus IDE Initialize Power Management Load alternate registers with initial POST values Restore CPU control word during warm boot Initialize PCI Bus Mastering devices Initialize keyboard controller BIOS ROM checksum Initialize cache before memory autosize timer initialization DMA controller initialization Reset Programmable Interrupt Controller Test DRAM refresh Test 8742 Keyboard Controller Set ES segment register to 4 GB Enable A20 line Autosize DRAM Initialize POST Memory Manager Clear 512 KB base RAM RAM failure on address line xxxx* RAM failure on data bits xxxx* of low byte of memory bus Enable cache before system BIOS shadow RAM failure on data bits xxxx* of high byte of memory bus Test CPU bus-clock frequency Initialize Phoenix Dispatch Manager Warm start shut down Shadow system BIOS ROM Autosize cache Chapter 4 135