Acer Aspire 7530 Aspire 7230/7530/7530G Service Guide - Page 163

POST Code 0x4C 0x59 0x57 0xD6 0x58 0x3F 0xC4 0x7C 0x41 0x4B 0xDE 0xC6 0x4E 0xD4 0x50 0xC9 0x51 0x5A 0x5B 0x5C 0x60 0x62 0x64 0x66 0x68 Function Shadow video BIOS ROM if specified by Setup, and CMOS is valid and the previous boot was OK. Register POST Display Services, fonts, and languages with the POST Dispatch Manager. Initialize 1394 Firewire Initialize PC card Test for unexpected interrupts. First do an STI for hot interrupts. Secondly, test the NMI for an unexpected interrupt. Thirdly, enable the parity checkers and read from memory, checking for an unexpected interrupt. ROMPolit memory init Install the IRQ vectors (Sever Hotkey) Initialize the hardware interrupt vectors from 08 to 0F and from 70h to 77H. Also set the interrupt vectors from 60h to 66H to zero. ROM Pilot Init Initialize QuietBoot if it is installed. Enable both keyboard and timer interrupts (IRQ0 and IRQ1). If your POST tasks require interrupts off, preserve them with a PUSHF and CLI at the beginning and a POPF at the end. Initialize and UNDI ROM (fro remote flash) Initial and install console for UCR Display copyright notice. Get CPU branding string Display CPU type and speed pretask before EISA init EISA Init Display prompt "Press F2 to enter SETUP" Disable CPU cache. Test RAM between 512K and 640K. Determine and test the amount of extended memory available. Determine if memory exists by writing to a few strategic locations and see if the data can be read back. If so, perform an address-line test and a RAM test on the memory. The amount of memory available. This test is dependent on the processor, since the test will vary depending on the width of memory (16 or 32 bits). This test will also use A20 as the skew address to prevent corruption of the system memory. Jump to UserPatch1. Set cache registers to their CMOS values if CMOS is valid, unless auto configuration is enabled, in which case load cache registers from the Setup default table. Enable external cache and CPU cache if present. Configure non-cacheable regions if necessary. Phase LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT Chapter 4 Component Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core 153