Acer Aspire 7530 Aspire 7230/7530/7530G Service Guide - Page 164

POST Code 0x6A 0x6C 0xCA 0x70 0x72 0x4F 0xCD 0x7D 0x7E 0xC1 0x80 0xCA 0x88 0x81 0x87 0x85 0x82 0x84 0x86 0x83 0xCE 0x89 0x8C 0xCB 0xCD 0x90 Function Display external cache size on the screen if it is nonzero. Display shadow message post EISA init Check flags in CMOS and in the TrustedCore data area for errors detected during POST. Display error messages on the screen. Check status bits to see if configuration problems were detected. If so, display error messages on the screen. Initialize MultiBoot. Allocate memory for old and new MultiBoot history tables. Reclaim console vector after HW vectors initialized. Initialize Intelligent System Monitoring. The Coprocessor initialization test. Use the floating point instructions to determine if a coprocessor exists instead of the ET bit in CR0. Check Boot Type (Server BIOS) Disable onboard COM and LPT ports before testing for presence of external I/O devices. Redirect Int 15h to enable target board to use remote keyboard (PICO BIOS). Initialize interrupt controller. Run late device initialization routines. Initialize motherboard configurable devices. Display any ESCD read errors and configure all PnP ISA devices. Test and identify RS232 ports. Test and identify parallel ports. Initialize onboard I/O and BDA according to CMOS and presence of external devices. Configure Fisk Disk Controller. Initialize digitizer device and display installed message if successful. Enable non-maskable interrupts. Initialize both of the floppy disks and display an error message if failure was detected. Check both drives to establish the appropriate diskette types in the TrustedCore data area Redirect Int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk (PICO BIOS). Remap I/O and memory address space for PCMCIA (PICO BIOS). Initialize hard-disk controller. If the CMOS ram is valid and intact, and fixed disks are defined, call the fixed disk init routine to initialize the fixed disk system and take over the appropriate interrupt vectors. Phase LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT 154 Component Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Chapter 4