Acer Aspire M3-581TG Acer Aspire M3-581T and M3-581TG Notebook Service Guide - Page 187

Table 4-3. SEC Phase POST Code Table (Continued) Functionality Name (Include\ PostCode.h) SEC_SETUP_CAR_OK SEC_FORCE_MAX_RATIO* Phase SEC SEC SEC_GO_TO_SECSTARTUP SEC_GO_TO_PEICORE SEC SEC * 3rd party relate functions - Platform dependence. Post Code 7 8 9 0A Description Cache as RAM test Tune CPU frequency ratio to maximum level Setup BIOS ROM cache Enter Boot Firmware Volume Table 4-4. PEI Phase POST Code Table Functionality Name (Include\ PostCode.h) PEI_SIO_INIT PEI_CPU_REG_INIT PEI_CPU_AP_INIT* PEI_CPU_HT_RESET* PEI_PCIE_MMIO_INIT PEI_NB_REG_INIT PEI_SB_REG_INIT PEI_PCIE_TRAINING* PEI_TPM_INIT PEI_SMBUS_INIT PEI_PROGRAM_CLOCK_GEN PEI_IGD_EARLY_INITIAL * PEI_HECI_INIT* PEI_WATCHDOG_INIT* PEI_MEMORY_INIT PEI_MEMORY_INIT_FOR_CRISIS PEI_MEMORY_INSTALL PEI_TXTPEI* PEI_SWITCH_STACK PEI_MEMORY_CALLBACK Phase PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI Post Code 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 Description Super I/O Initialization CPU Early Initialization Multi-processor Early Initial HyperTransport Initialization PCIE MMIO BAR Initialization North Bridge Early Initialization South Bridge Early Initialization PCIE Training TPM Initialization SMBUS Early Initialization Clock Generator Initialization Internal Graphic device early Initialization HECI Initialization Watchdog timer Initialization Memory Initial for Normal boot. Memory Initial for Crisis Recovery Simple Memory test TXT function early Initialization Start to use Memory Set cache for physical memory Troubleshooting 4-21