Acer Power F5 Aspire T650/E500 and Power F5 Service Guide - Page 9

Supports HS 480Mbits/sec, FS 12Mbits/sec and LS, One EHCI USB 2.0 and three OHCI USB 1.1 Host - sata

Page 9 highlights

Chipset ULI M1573 REALTEK ALC880 Controller Marvell 8EE8001 GigaLAN ITE IT8712 Controller 2 General Features T Provides a High Integration Bridge T One EHCI USB 2.0 and three OHCI USB 1.1 Host Controllers for supporting up to eight USB ports T Supports HS (480Mbits/sec), FS (12Mbits/sec) and LS (1.5Mbits/sec) data transfer rate T Provides High Definition(HD) Audio/AC'97 2.3 compliant digital controller interface for third parties (such as the AMC Codec's vendor) to enable the software modem solution T Provides 1/10/100 Mbps Medium Access Control (MAC) controller for the best solution of the phone-line/ Ethernet LAN connectivity T Supports SATA 1.0 (High Speed Serialized AT Attachment, Revision 1.0a), 1.5 Gb/s data rate T High-performance DACs with 100dB S/N ratio T ADCs with S/N ratio greater than 85dB T 8 DAC channels support 16/20/24-bit PCM format for 7.1 audio solution T Supports 44.1K/48K/86K/192KHz DAC sample rate T All ADCs support 44.1K/48K/96K sample rate T -64dB ~ +30dB with 1dB resolution of mixer gain to achieve finer volume control T Emulation of 26 sound environments to enhance gaming experience T 10 Software Equalizer Bands T Integrated 10/100/1000 transceiver T Wake-on-LAN and remote wake-up support T Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab T Supports IEEE 802.1Q VLAN tagging T Supports up to 1/240 duty cycle T Provides 320 LCD drive circuits T Provides 2.6 to 5.5V LCD drive voltage T Provides 2.5 to 5.5V operating voltage T Provides 4-bit or 8-bit parallel data input T Supports screen display off function T Supports the automatic generation of chip enable sign T Supports Power standby function T Package : Flex-TCP /can also be shipped in CHI (433 bumps) T Maximum shirt clock frequency : 6.5 MHz (VCC=3V)/8 MHz (VCC=5V) T Two output modes are selectable : 320 output mode/ 240 output mode Chapter 1

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