Acer Veriton 7500 Veriton 5500/7500 Service Guide - Page 73

Parameter, Description, Option, By SPD, Enabled, Disabled, 128MB, register, FWH, and LPC I/F accesses.

Page 73 highlights

. Parameter DRAM Timing Selectable Description SDRAM Timing By SPD Manual Option CAS Latency Time The default setting by your DRAM's SPD. Active to Precharge Delay The default setting by your DRAM's SPD. 1.5/2/2.5/3 7/6/5 DRAM RAS #to CAS# Delay The default setting by your DRAM's SPD. 3/2 DRAM RAS# Precharge The default setting by your DRAM's SPD. 3/2 Memory Frequency fo Memory frequency default setup. Auto/ DDR200/DDR266 System BIOS Cacheable E.F segment shadow RAM cacheable. Enabled/Disabled Video BIOS Cacheable C segment shadow RAM cacheable. Enabled/Disabled Video RAM Cacheable A.B segment shadow RAM cacheable. Disabled/Enabled Memory Hole at 15M-16 The system will reserve 15-16 MB address for the add-on card. Disabled/Enabled Delayed Transaction ICH4 enables delayed transactions for internal register, FWH, and LPC I/F accesses. Enabled/Disabled Delay Prior to Thermal Enables Pentium 4 thermal function - 16 miuntes 16/4/8/32 minutes after POST.(only for ACPI OS AGP Aperture Size (MB) Aperture size: the size of the system memory for 64/4/8/16/32/128/256 AGP card. Options to decide how many size for AGP card. On-Chip Video Window size Aperture size for on-board CPU. 128MB/64MB/Disabled On-Chip Frame Buffer size Frame buffer size for on-chip VGA. 8MB/1MB/512MB Integrated Peripherals 65 Veriton 3500/5500/7500

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