Acer X1200 ED5200A Aspire X1200 / X3200 Service Guide - Page 23

Advanced Chipset Features Parameter Hyper SLI iGPU Frame Buffer Control Frame Buffer Size CPU Frequency KBNB HT Speed KBNB HT Width PCIE Clock DRAM Configuration CPU Spread Spectrum PCIE Spread Spectrum SATA Spread Spectrum Description Option Enable or disable the Scalable Link Interface (SLI) technology. Disabled Enabled When set to auto, BIOS will automatically setup the frame buffer size. When set to manual, you can set the frame buffer size. Frame buffer size is the total amount of system memory allocated solely for the onboard graphics controller. Auto Manual This parameter can be configured if the iGPU Frame Buffer Control is 64, 16, 32, 128, set to Manual. 256 MB Sets processor minimum and maximum frequency. 200 Minimum 100 Maximum 500 Controls the physical speed of the processor to the Northbridge HT link. Auto 200, 400, 600, 800 MHz, 1 GHz Controls the processor to the Northbridge link bandwidth. Auto Up 8/16 Down 8/16 Sets the PCI Express clock frequency. 100 Minimum 100 Maximum 200 Press Enter to configure memory timing and operation settings. Allows you to reduce the EMI of the front side bus by modulating the signals it generates so that the spikes are reduced to flatter curves. Disabled -0.5%, 1.0% Allows you to reduce the EMI of the PCI Express bus by modulating the signals it generates so that the spikes are reduced to flatter curves. When set to down spread, the chipset modulates the PCI Express bus' baseline signal downwards by a small amount. When set to disabled, the chipset disables any modulation of the PCI Express bus' baseline signal. Disabled Down Spread Allows you to reduce the EMI of the SATA bus by modulating the signals it generates so that the spikes are reduced to flatter curves. When set to down spread, the chipset modulates the SATA bus' baseline signal downwards by a small amount. When set to disabled, the chipset disables any modulation of the SATA bus' baseline signal. Disabled Down Spread Chapter 2 15