Acer X1200 ED5200A Aspire X1200 / X3200 Service Guide - Page 24

Parameter iGPU Spread Spectrum SSE/SSE2 Instructions MCP78 PCIE Training System BIOS cacheable Description Allows you to set the integrated GPU spread spectrum. Enables or disables the processor's SSE and SSE2 instruction sets. Cards supporting Gen2 mode will be trained in Gen2 mode. Enables or disables the caching of the mainboard BIOS ROM from F0000h to FFFFFh by the processor's Level 2 cache. Option 50 Triangular Cntr 100/200/300 Triangular Cntr Enabled Disabled Gen2 if supported Only Gen1 Disabled Enabled 16 Chapter 2