Acer AS5534-1121 Aspire 5534 Service Guide - Page 176

POST Code Tables These tables describe the POST codes and descriptions during the POST. Sec NO_EVICTION_MODE_DEBUG EQU 1 (CommonPlatform\sec\Ia32\SecCore.inc) Post Code 0xC2 0xC3 0xC4 0xC5 0xCF Description MTRR setup Enable cache Establish cache tags Enter NEM, Place the BSP in No Fill mode, set CR0.CD = 1, CR0.NW = 0. Cache Init Finished Memory DEBUG_BIOS equ 1 (Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC) Post Code 0xA0 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x20 0x21 0x22 0x23 0x24 0x25 0x26 Description First memory check point Enable MCHBAR Check for DRAM initialization interrupt and reset fail Verify all DIMMs are DDR or DDR2 and unbuffered Detect an improper warm reset and handle Detect if ECC SO-DIMMs are present in the system Verify all DIMMs are single or double sided and not asymmetric Verify all DIMMs are x8 or x16 width Find a common CAS latency between the DIMMS and the MCH Determine the memory frequency and CAS latency to program Determine the smallest common TRAS for all DIMMs Determine the smallest common TRP for all DIMMs Determine the smallest common TRCD for all DIMMs Determine the smallest refresh period for all DIMMs Verify burst length of 8 is supported by all DIMMs Determine the smallest tWR supported by all DIMMs Determine DIMM size parameters Program the correct system memory frequency Determine and set the mode of operation for the memory channels Program clock crossing registers Disable Fast Dispatch Program the DRAM Row Attributes and DRAM Row Boundary registers Program the DRAM Bank Architecture register Program the DRAM Timing & and DRAM Control registers Program ODT Perform steps required before memory init Program the receive enable reference timing control register Chapter 4 166