Acer Aspire 5750 Service Guide - Page 159

Post Codes 0 The following tables describe the POST codes and descriptions during the POST. Table 4-2. NO_EVICTION_MODE_DEBUG EQU 1 (CommonPlatform\sec\Ia32\SecCore.inc) Phase POST Code Range 0xC2 MTRR setup 0xC3 Enable cache 0xC4 Establish cache tags nf 0xC5 Enter NEM, Place the BSP in No Fill mode, set CR0.CD = 1, CR0.NW = 0. 0xCF Cache Init Finished Table 4-3. DEBUG_BIOS equ 1 (Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC) Phase POST Code Range 0xA0 0x01 0x02 0x03 First memory check point Enable MCHBAR o Check for DRAM initialization interrupt and reset fail Verify all DIMMs are DDR or DDR2 and unbuffered 0x04 0x05 0x06 Detect an improper warm reset and handle eS Detect if ECC SO-DIMMs are present in the system Verify all DIMMs are single or double sided and not asymmetric 0x07 0x08 0x09 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x30 Verify all DIMMs are x8 or x16 width Find a common CAS latency between the DIMMS and the MCH Determine the memory frequency and CAS latency to program Program the DRAM Bank Architecture register Program the DRAM Timing & and DRAM Control registers Program ODT Perform steps required before memory init oft Program the receive enable reference timing control register Program the DLL Timing Control Registers, RCOMP settings Se Enable DRAM Channel I/O Buffers Enable all clocks on populated rows Perform JEDEC memory initialization for all memory rows Perform steps required after memory init http://Tmroyucbloesmhopo.tsinug 4м-2а5