Acer Aspire M5-481PT Acer Aspire M5-481T, PT, and TG Notebook Service Guide - Page 180

Post Codes 0 The following are the InsydeH2O™ Functionality POST code tables. The components of the POST code table includes: SEC phase, PEI phase, DXE phase, BDS phase, CSM functions, S3 functions and ACPI functions. Post Code Range Phase POST Code Range SEC PEI 0x01 - 0x0F 0x70 - 0x9F DXE BDS 0x40 - 0x6F 0x10 - 0x3F SMM 0xA0 - 0xBF S3 ASL PostBDS 0xC0 - 0xCF 0x51 - 0x55 0xE1 - 0xE4 0xF9 - 0xFE InsydeH2ODDT™ Reserve 0xD0 - 0xD7 OEM Reserve Reserved 0xE8 - 0xEB 0xD8 - 0xE0 0xE5 - 0xE7 0xEC - 0xF8 SEC Phase Post Code Functionality Name (Include\PostCode.h) SEC_SYSTEM_POWER_ON SEC_BEFORE_MICROCODE_PATCH SEC_AFTER_MICROCODE_PATCH SEC_ACCESS_CSR* SEC_GENERIC_MSRINIT* SEC_CPU_SPEEDCFG* SEC_SETUP_CAR_OK SEC_FORCE_MAX_RATIO* SEC_GO_TO_SECSTARTUP Phase SEC SEC SEC SEC SEC SEC SEC SEC SEC Post Code 01 02 03 04 05 06 07 08 09 Description CPU power on and switch to Protected mode Patching CPU microcode Setup Cache as RAM PCIE MMIO Base Address initial CPU Generic MSR initialization Setup CPU speed Cache as RAM test Tune CPU frequency ratio to maximum level Setup BIOS ROM cache Troubleshooting 4-15