Acer Aspire T320 Aspire T320 Service Guide - Page 65

POST Check Points When POST executes a task, it uses a series of preset numbers called check point to be latched at port 80h, indicating the stages it is currently running. This latch can be read and shown on a debug board. The following table describes the Acer common tasks carried out by POST. A unique check point number represents each task. Checkpoint CFh C0h C1h C3h C5h 0h1 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h Chapter 4 Description Test CMOS R/W functionality Early chipset initialization: • Disable shadow RAM • Disable L2 Cache (socket 7 or below) • Program basic chipset registers Detect memory • Auto-detection of DRAM size, type and ECC. • Auto-detection of L2 cache (socket 7 or below) Expand compressed BIOS code to DRAM Call chipset hook to copy BIOS back to E000 & F000 shadow RAM Expand the Xgroup codes locating in physical address 1000:0 Reserved Initial Superio_Early_Init switch Reserved 1. Blank out screen 2. Clear CMOS error flag Reserved 1. Clear 8042 interface 2. Initialize 8042 self-test 1. Test special keyboard controller for Winbond 977 series Super I/O chips 2. Enable keyboard interface Reserved 1. Disable PS/2 mouse interface (optional) 2. Auto detect ports for keyboard & mouse followed by a port & inter- face swap (optional) 3. Reset keyboard for Winbond 977 series Super I/O chips Reserved Reserved Reserved Test F000h segment shadow to see whether it is R/W-able or not. If test fails. keep beeping the speaker. Reserved Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for ESCD & DMI support. Reserved Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override. Reserved 58