Acer Aspire X3400G Acer Aspire X3400, X3400G Desktop Service Guide - Page 61

Checkpoints A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the preboot process. Viewing BIOS checkpoints Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a POST card or POST diagnostic card. These are ISA or PCI add-in cards that show the value of I/O port 80h on a LED display. Checkpoints may appear on the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset, memory, and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS. NOTE: Please note that checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices. Checkpoint Before D1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA Description Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. NMI is disabled. Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum. Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS. Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled. If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled. Test base 512KB memory. Adjust policies and cache first 8MB. Set stack. Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section for more information. Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash. The Runtime module is uncompressed into memory. CPUID information is stored in memory. Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM. Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section for more information. Chapter 4 53