Acer Aspire X3400G Acer Aspire X3400, X3400G Desktop Service Guide - Page 62

Bootblock Recovery Code Checkpoints, Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM. - only starts off and on

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Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS. NOTE: Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices. Checkpoint E0 E9 EA EB EF E9 or EA F0 F1 F2 F3 F5 FA FB F4 FC FD FF Description Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled. Set up floppy controller and data. Attempt to read from floppy. Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM. Disable ATAPI hardware. Jump back to checkpoint E9. Read error occurred on media. Jump back to checkpoint EB. Determine information about root directory of recovery media. Search for pre-defined recovery file name in root directory. Recovery file not found. Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file. Start reading the recovery file cluster by cluster. Disable L1 cache. Check the validity of the recovery file configuration to the current configuration of the flash part. Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size. The recovery file size does not equal the found flash part size. Erase the flash part. Program the flash part. The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h. 54 Chapter 4

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