Gigabyte GA-8N-SLI Quad Royal Manual
Gigabyte GA-8N-SLI Quad Royal Manual
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Gigabyte GA-8N-SLI Quad Royal manual content summary:
- Gigabyte GA-8N-SLI Quad Royal | Manual - Page 1
Auto-Configuration C3h Expand compressed BIOS code to DRAM C5h Call chipset hook to copy BIOS back to E000 & F000 support. 12h Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override. GA-8N-SLI Quad Royal - Gigabyte GA-8N-SLI Quad Royal | Manual - Page 2
speed Invoke video BIOS. 1. Initialize multi-language 2. Put information on screen display, including Award title, CPU type, CPU speed .... Reset keyboard except Winbond 977 series Super I/O chips. Test 8254 Test 8259 interrupt mask bits for channel 1. GA-8N-SLI Quad Royal Post Code Definition - Gigabyte GA-8N-SLI Quad Royal | Manual - Page 3
last double word of each 64K page. 2. Program write allocation for AMD K5 CPU. 1. Program MTRR of M1 CPU 2. Initialize L2 cache utility; i.e. not until this POST stage can users enter the CMOS setup utility. Initialize PS/2 Mouse drive. GA-8N-SLI Quad Royal Post Code Definition 11/14/2005 3 - Gigabyte GA-8N-SLI Quad Royal | Manual - Page 4
parallel ports. Detect & install co-processor 1. Switch back to text mode if full screen logo is supported. -If errors occur, report errors & wait for keys -If no errors occur or F1 key is 20h or 19h 4. Load CMOS time into DOS timer tick GA-8N-SLI Quad Royal Post Code Definition 11/14/2005 4 - Gigabyte GA-8N-SLI Quad Royal | Manual - Page 5
POST (hex) FFh 5. Build MSIRQ routing table. Boot attempt (INT 19h) Description GA-8N-SLI Quad Royal Post Code Definition 11/14/2005 5
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GA-8N-SLI Quad Royal Post Code Definition
11/14/2005
1
GA-8N-SLI Quad Royal Post Code Definition
AWARD Post Code Definition
POST (hex)
Description
CFh
Test CMOS R/W functionality.
C0h
Early chipset initialization:
-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers
C1h
1. Detect memory
-Auto-detection of DRAM size, type and ECC.
-Auto-detection of L2 cache (socket 7 or below)
2. PEG slots Auto-Configuration
C3h
Expand compressed BIOS code to DRAM
C5h
Call chipset hook to copy BIOS back to E000 & F000 shadow
RAM.
0h1
Expand the Xgroup codes locating in physical address 1000:0
03h
Initial Superio_Early_Init switch.
05h
1. Blank out screen
2. Clear CMOS error flag
07h
1. Clear 8042 interface
2. Initialize 8042 self-test
08h
1.
Test special keyboard controller for Winbond 977 series Super
I/O chips.
2.
Enable keyboard interface.
0Ah
1.
Disable PS/2 mouse interface (optional).
2.
Auto detect ports for keyboard & mouse followed by a port & interface swap
(optional).
3.
Reset keyboard for Winbond 977 series Super I/O chips.
0Eh
Test F000h segment shadow to see whether it is R/W-able or not. If
test fails, keep beeping the speaker.
10h
Auto detect flash type to load appropriate flash R/W codes into the
run time area in F000 for ESCD & DMI support.
12h
Use walking 1’s algorithm to check out interface in CMOS
circuitry.
Also set real-time clock power status, and then check for
override.