HP 8550 Service Manual - Page 205

AP-IP (analog image processing) PCB The analog image processing circuit processes the output from the CCD for the following: l Odd- and even-number bit synthesis l BGR level matching l A/D conversion circuit l ABC circuit The image signals coming from the CCD in six channels are held for sampling by the sample hold signals (SH1 through SH4) for extracting signal components. Thereafter, BGR signal levels are matched according to the BGR gain and offset signals for correction of photo conversion efficiencies (of the B, G, and R CCD lines); then, the results are synthesized into B, G, and R image signals according to the select signal (SEL). The A/D conversion circuit operates in response to the ADCLK signal, and serves to convert B, G, and R image signals into 8-bit digital signals for input to the image processor block. Figure 95. Analog circuit EN Copy module 203