HP BL40p Memory technology evolution: an overview of system memory technologie
HP BL40p - ProLiant - 1 GB RAM Manual
UPC - 613326517680
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- HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 1
...2 DRAM storage density and power consumption 4 Memory access time ...5 System bus timing ...5 Memory bus speed...6 Burst mode access DIMMs ...19 Rambus DRAM ...21 Importance of using HP-certified memory modules in ProLiant servers 23 Conclusion...23 For more information...24 Call to action ...24 - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 2
ProLiant servers. This paper summarizes the evolution of memory technology and provides an overview of some the newest memory technologies that HP is evaluating for servers from system memory. This performance gap prevents many applications from effectively using the full computing power of modern - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 3
Each DRAM chip contains millions of memory locations (or cells), which are arranged in a matrix of rows and columns (Figure 1). Peripheral circuitry on the DIMM reads, amplifies, and transfers the data from the memory cells to the memory bus. Each DRAM row, called a page, consists of several DRAM - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 4
components was originally 5 volts. However, as cell geometries decreased, memory circuitry became smaller and more sensitive. Likewise, the industry-standard operating voltage decreased. Today, computer memory components operate at 1.8 volts, which allows them to run faster and consume less power. 4 - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 5
memory access time is measured by the number of memory bus clocks. System bus timing A system bus clock controls all computer components that execute instructions others have. For this reason, the components in a typical server are controlled by different clocks that run at different, but related - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 6
memory subsystem are the memory timing and the maximum DRAM speed. The server BIOS sets the memory memory access. During memory access, first the RAS and CAS and then 64 bits of data were transferred through the memory memory sections of memory are 64-bit memory sections. With the memory controller - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 7
notches that prevent incorrect installation and indicate the type of DRAM module. Figure 5. SDRAM DIMM with two notches Bank interleaving SDRAM divides memory into two to four banks for simultaneous access to more data. This division and simultaneous access is known as interleaving. Using a notebook - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 8
The ninth chip is used to store 4 bits or 8 bits of Error Correction Code (ECC). An ECC DIMM with all nine DRAM chips on one side is called , DIMMs are classified as to rank. A memory rank is defined as an area or block of 64-bits (72 bits for ECC memory) created by using some or all of the - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 9
slots exceeds the maximum number of loads the chipset can support, the server may not boot properly or it may not operate reliably. Some systems check the memory configuration while booting to detect invalid memory bus loading. When an invalid memory configuration is detected, the system stops the - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 10
operating systems to address more memory, which causes manufacturers to expand the memory capacity of the servers. For example, while the HP ProLiant DL585 G2 of 2007 could support a maximum of 128 GB, some of the latest servers now support up to 256 GB of memory. As manufacturers continue to expand - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 11
memory errors or detect multi-bit errors. HP introduced error correction code (ECC) memory in 1993 and continues to implement advanced ECC in all HP ProLiant servers DRAM chip. ECC memory responds to these multibit errors by generating a non-maskable interrupt (NMI) that instructs the system to halt - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 12
not provide failover capability. As a result, if there is a memory failure, the system must be shut down before the memory can be replaced. The latest generation of HP ProLiant servers offers two levels of Advanced Memory Protection that provide increased fault tolerance for applications requiring - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 13
to the associated server user guide. In a system with three channels per memory controller, two channels operate normally and the third channel is the spare. Online Spare mode does not require operating system support or special software beyond the System BIOS. However, to support messaging and - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 14
. A server can remain up and running until it is convenient to take the equipment offline and down for servicing. However, memory protection modes desired memory protection mode through the ROM-based Setup Utility (RBSU) contained in the BIOS. Online Spare, Mirrored, and Lockstep memory protection - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 15
doubles the transfer rate without increasing the frequency of the memory clock. This section describes three generations of DDR SDRAM rate, DDR SDRAM uses a technique called prefetching to transfer two bits from the memory cell array to the I/O buffer in two separate pipelines. Then the I/O - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 16
Logic_2 (SSTL_2). This low-voltage signaling results in lower power consumption and improved heat dissipation. Stobe-based data bus a data strobe signal as data becomes valid on the SDRAM pins. The memory controller uses the data strobe signal to locate data more accurately and resynchronize incoming - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 17
for use in desktop PCs or servers. To vary the cost of DDR-1 DIMMs for these different markets, memory manufacturers provide unbuffered and registered versions to 6.4 GB/s, lower power consumption, and improvements in packaging. At 400 MHz and 800 Mb/s, DDR-2 increases memory bandwidth to 6.4 GB/s- - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 18
feature requires the controller to support "write leveling" on DDR-3 DIMMs. 1.5-V signaling reduces power consumption even further than 1.8 UDIMMs represent the most basic type of memory module and offer lower latency and (relatively) low power consumption but are limited in capacity. Unbuffered - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 19
a stub-bus topology with parallel branches (stubs) that connect to a shared memory bus (Figure 15). Each DIMM connects to the data bus using a set can result in circuitous traces on the motherboard between the memory controller and memory slots. Both the latency resulting from complex routing of - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 20
DIMMs per channel that can be supported as the bus speed increases. For example, Figure 16 shows the number of loads supported per channel at data rates ranging servers, neither option was acceptable. Future generations of servers require improved memory architecture to achieve higher memory - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 21
pulse. RDRAM uses a separate row and column command bus that allows issuing multiple commands at the same time, thereby increasing the bandwidth efficiency of the memory bus. This dual command bus is a unique feature of RDRAM. With only an 8-bit-wide command bus and an 18-bit data bus, RDRAM (Figure - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 22
communicates only with the repeater chips. Up to eight repeater chips can be placed on the memory controller, and 32 RDRAM devices can be placed on each channel. This allows one channel to support a maximum of 256 devices. However, using the repeater chips will add 1 to 1.5 clocks of additional - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 23
option kits precisely match the capabilities and requirements of the ProLiant server for which they are designated. HP memory option kits are listed in each server's user guide and in the product QuickSpecs available at www.hp.com. Conclusion The increasing performance gap between processors and - HP BL40p | Memory technology evolution: an overview of system memory technologie - Page 24
HP ProLiant servers Web address http://www.jedec.org http://h18004.www1.hp.com/products/servers/technology HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP
Abstract
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2
Introduction
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2
Basic DRAM operation
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2
DRAM storage density and power consumption
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4
Memory access time
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5
System bus timing
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5
Memory bus speed
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6
Burst mode access
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6
SDRAM technology
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7
Bank interleaving
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7
Increased bandwidth
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7
Registered SDRAM modules
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8
DIMM configurations
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8
Single-sided and double-sided DIMMs
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8
Single-rank, dual-rank, and quad-rank DIMMs
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8
DIMM error detection/correction technologies
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10
The increasing possibility of memory errors
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10
Basic ECC memory
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11
Advanced ECC memory
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12
Memory protection technologies
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13
Online spare memory mode
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13
Mirrored memory mode
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13
Lockstep memory mode
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14
Memory protection mode summary
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14
Advanced memory technologies
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15
Double data rate SDRAM technologies
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15
DDR-1
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15
DDR-2
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17
DDR-3
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18
Module naming convention and peak bandwidth
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18
Fully-buffered DIMMs
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19
Rambus DRAM
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21
Importance of using HP-certified memory modules in ProLiant servers
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23
Conclusion
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23
For more information
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24
Call to action
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24
Memory technology evolution:
an overview of system memory technologies
technology brief, 8
th
edition