HP DL360 ISS Technology Update, Volume 7, Number 7

ISS Technology Update

Volume 7, Number 7

Keeping you informed of the latest ISS technology

The influence of memory latency and bandwidth on system performance

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1

Meet the Expert—Vincent Nguyen

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3

Soft memory errors caused by natural phenomena

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4

Spotlight: HP Microsoft Solutions Lab benefits customers, partners,

and resellers

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5

Overview of Microsoft® Windows® Essential Server Solutions

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7

Recently published industry standard server technology communications

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11

Contact us

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The influence of memory latency and bandwidth on system performance

Slow application response can cause an end user to experience anything from a frustrating delay to a missed opportunity in a

split-second financial transaction. Part of the problem could be that the application is not optimized for the server, or vice versa.

One example is when a single-threaded application runs on a server with multi-core processors (See “Multi-core Technology” in

Volume 7, Number 6 of the

ISS Technology Update

).

Alternatively, slow application response can occur while the processor is waiting for data from system memory, commonly

referred to as memory latency. Memory latency is the time it takes for non-cached data to be retrieved from synchronous

dynamic random access memory (SDRAM) after a READ request from the processor. This time is measured in bus clock cycles,

with each clock cycle lasting a few billionths of a second, or nanoseconds. Although latency is measured in nanoseconds, it has

a relatively significant impact on system performance. In fact, system designers have found that a two percent reduction in

memory latency can cause a one percent improvement in system performance for some database applications. Conversely,

excessive latency can cause the processor to stall as it waits for data, bringing the entire system to a crawl.

As shown in Figure 1, the total response time consists of flight time of the read request on the front side bus (FSB), propagation

delay through the memory controller, flight time on the memory bus, response time of the SDRAM, and the time it takes for data

to travel back to the processor. Flight time is the time it takes for commands and data to travel along the FSB and memory bus.

Flight time is affected by the operating frequency of the buses.

The response time of the SDRAM is the delay, in clock cycles, while retrieving the data and driving it to the SDRAM pins on the

bus. This delay is also referred to as CAS latency (see right column: “SDRAM operation”).