HP ML115 The AMD processor roadmap for industry-standard servers, 6th edition
HP ML115 - ProLiant - G5 Manual
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- HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 1
...8 Quad-Core AMD Opteron processors 9 AMD Smart Fetch Technology ...10 Enhanced AMD PowerNow! Technology 10 Rapid Virtualization Indexing...10 Average CPU Power metric ...11 Independent and combined memory channel modes 12 Six-Core AMD Opteron processors 12 HT Assist ...13 Future AMD Opteron - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 2
this requires the OS and applications to take advantage of the additional memory addressing. AMD Opteron processors support 32-bit addressing as well as the 36-bit PAE. As shown in Table 1, the x86, 32-bit instruction set of the AMD Opteron family of processors includes the following: • Standard x86 - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 3
applications. The most important feature of AMD64 is support for very large virtual and physical memory in a flat address space. Instruction set and registers AMD64 instructions can take advantage of the 64-bit wide registers in AMD Opteron processors. These registers are used by the applications - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 4
processors support up to 48 bits (256 Terabytes) for physical memory and use 64 bits for virtual memory Naming conventions First-generation single-core AMD Opteron processors (Socket 940 and Socket 939) have three-digit model numbers in the form XZZ, and third-generation Quad-Core AMD Opteron - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 5
HyperTransport Technology links and an integrated memory controller connected to dedicated memory banks for each processor. Integrated memory controller and dedicated memory banks Each AMD Opteron processor contains an integrated dual-channel SDRAM memory controller that is directly connected to - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 6
and I/O traffic and directly attaches memory to each processor, allowing memory capacity to scale with the number of processors. 4 HyperTransport Technology was invented at AMD with contributions from industry partners and is managed and licensed by the HyperTransport Technology Consortium, a Texas - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 7
) and Socket AM2 designs support dual-core AMD Revision F processors. The primary difference between the processors designed for single, dual, or multi-core systems is in the way the processor uses the HyperTransport link(s). In the 1000 series AMD Opteron processors, the single HyperTransport link - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 8
within the same power and thermal envelopes.7 6 AMD whitepaper "Multi-Core Processors-The Next Evolution in Computing" is accessible at http://multicore.amd.com/Resources/33211A_Multi-Core_WP_en.pdf. 7 HP ProLiant DL145 G3 servers do not support quad-core Revision F processor upgradeability. 8 - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 9
new core microarchitecture - K8L (true quad-core on a single die) • Extensions to AMD64 instruction set - bit manipulation and SSE, SSE2, SSE3, and SSE4 • 128-bit FPU for improved floating point and graphics performance • AMD Smart Fetch Technology Support for DDR2 memory • Dedicated 64-KB L1 cache - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 10
Enhanced AMD PowerNow! Technology Native quad-core technology enables enhancements to AMD PowerNow! Technology across all four cores. Two power Power Management Dual Dynamic Power Management provides separate (split) power planes for the cores and memory controller. This can reduce idle power - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 11
Indexing is the AMD implementation of nested page tables technology which allows virtual machines to manage memory more directly. From these test results, AMD developed an average CPU power (ACP) metric to more accurately estimate the power consumption of AMD Opteron processors during peak workloads - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 12
(watts) 137 Average CPU Power (watts) 105 115 75 75 55 Independent and combined memory channel modes The Quad-Core AMD Opteron processor includes two DRAM controllers that support DDR2 DIMMs. Each DRAM controller controls one 64-bit DDR DIMM channel that connects to a series of DIMMs. The DRAM - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 13
AMD Opteron processor operates in the same power and thermal envelope as the Quad-Core Opteron processor while improving performance by up to 50%. HT Assist HT Assist helps increase performance of six-core AMD Opteron protocol and only requests data from system memory is there is a cache miss. All - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 14
ProLiant servers using the AMD Opteron processor family have proven their performance in numerous benchmarks and systems. Multi-core AMD Opteron technology takes advantage of multi-threaded applications and reduces latencies, providing higher performance within the same power budget. 8 Refer to the - HP ML115 | The AMD processor roadmap for industry-standard servers, 6th edition - Page 15
contained herein. AMD and AMD Opteron are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Intel is a registered trademark and Xeon is a trademark of Intel Corporation in the U.S. and other countries. TC091005TB, October
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The AMD processor roadmap for industry-
standard servers
technology brief, 6th Edition
Abstract
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2
Introduction
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2
X86 architecture
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2
32-bit operations
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2
AMD64 technology
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3
Instruction set and registers
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3
Operating modes
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4
Memory addressability
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4
Naming conventions
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4
Direct Connect I/O Architecture
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5
Integrated memory controller and dedicated memory banks
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5
HyperTransport Technology
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6
Multi-core technologies
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7
Dual-core Revision F processors
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8
Quad-Core AMD Opteron processors
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AMD Smart Fetch Technology
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10
Enhanced AMD PowerNow! Technology
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10
Rapid Virtualization Indexing
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10
Average CPU Power metric
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11
Independent and combined memory channel modes
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12
Six-Core AMD Opteron processors
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12
HT Assist
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13
Future AMD Opteron processors
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Software licensing
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Conclusion
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For more information
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Call to action
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