HP ProLiant SL170s Memory technology evolution: an overview of system memory t
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- HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 1
DDR-3 ...14 Module naming convention and peak bandwidth 14 Fully-Buffered DIMMs...15 FB-DIMM architecture...16 Challenges ...17 Rambus DRAM ...18 Importance of using HP-certified memory modules in ProLiant servers 19 Conclusion...19 For more information...20 Call to action ...20 - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 2
developing memory technologies in terms of price, performance, and backward compatibility and implements the most promising technologies in ProLiant servers. HP is committed to providing customers with the most reliable memory at the lowest possible cost. This paper summarizes the evolution - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 3
/command bus is a set of traces that carry signals identifying the location of data in memory. The command portion of the address/command bus conveys instructions such as read, write, or refresh. When FPM or EDO memory writes data to a particular cell, the location where the data will be written is - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 4
bus clocks. Chipsets and system bus timing All computer components that execute instructions or transfer data are controlled by a system bus clock. The two voltages (designated as "0" and "1" in Figure 3) at a specific frequency. The bus frequency is measured in millions of cycles per second, - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 5
more than others have. For this reason, the components in a typical server are controlled by different clocks that run at different, but related, speeds must wait one or more additional clock cycles for data or instructions due to clock resynchronization. In contrast, synchronized components know on - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 6
with every clock cycle after the first access (6-1-1-1) before the memory controller has to send another CAS. Figure 4. Burst mode access. NOP is a "No Operation" instruction. Clock Command Address Data Active NOP NOP Read NOP NOP NOP NOP NOP NOP Row Col Data Data Data Data 64b 64b 64b 64b - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 7
Bank interleaving SDRAM divides memory into two to four banks for simultaneous access to more data. This division and simultaneous access is known as interleaving. Using a notebook analogy, two-way interleaving is like dividing each page in a notebook into two parts and having two assistants to each - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 8
DIMM Configurations Single-sided and double-sided DIMMs Each DRAM chip on a DIMM provides either 4 bits or 8 bits of a 64-bit data word. Chips that provide 4 bits are called x4 (by 4), and chips that provide 8 bits are called x8 (by 8). It takes eight x8 chips or sixteen x4 chips to make a 64-bit - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 9
the maximum number of loads the chipset can support, the server may not boot properly or it may not problems, customers should only use HP-certified DIMMs available in the memory option kits for each ProLiant server (see the "Importance of using HP-certified memory modules in ProLiant servers - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 10
Memory channel interleaving Multi-core processors running multi-threaded applications pose a significant challenge to the memory subsystem. The processor cores share the bandwidth of the memory bus; therefore, the multi-core processor's performance is limited by the memory bus bandwidth. Even with - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 11
Advanced memory technologies Despite the performance improvement in the overall system due to use of SDRAM, the growing performance gap between the memory and processor must be filled by more advanced memory technologies. These technologies, which are described on the following pages, boost the - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 12
difference between SDRAM and DDR-1 is the signaling technology. Instead of using a 3.3-V operating voltage, DDR-1 uses a 2.5-V signaling specification known as Stub Series-Terminated Logic_2 (SSTL_2). This low-voltage signaling results in lower power consumption and improved heat dissipation. Stobe - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 13
DIMMs. DDR-1 is versatile enough to be used in desktop PCs or servers. To vary the cost of DDR-1 DIMMs for these different markets, memory many SDRAM devices are on the module. Therefore, they are best suited for servers with very high memory capacities. Figure 11. The 184-pin DRR-1 Registered DIMM - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 14
signals, and clocks) improves signal integrity by reducing the number of stubs and their length. This feature requires the controller to support "write leveling" on DDR-3 DIMMs. • 1.5-V signaling (compared to 1.8 V for DDR-2) for lower power consumption • A thermal sensor integrated on the DIMM - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 15
factors decrease the number DIMMs per channel that can be supported as the bus speed increases. For example, Figure 14 shows the number of loads supported per channel at data rates ranging from PC 100 to density. For future generations of high-performance servers, neither option was acceptable. 15 - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 16
Consequently, JEDEC developed the Fully-Buffered DIMM (FB-DIMM) specification, a serial interface that eliminates the parallel stub-bus topology and allows higher memory bandwidth while maintaining or increasing memory capacity. FB-DIMM architecture The FB- - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 17
get hotter. Therefore, a heat spreader is required to help draw heat away from the FB-DIMM so it can be cooled more efficiently by the server's internal fans (Figure 16). These concerns are driving the design of AMBs that use 15 to 20 percent less power, even though some manufacturers claim - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 18
consists of three key elements: RDRAMs, Rambus application-specific integrated circuits, and an interconnect called the Rambus the design of the memory controller. Figure 17. Rambus DRAM RDRAM is capable of supporting up to 32 RDRAM devices on one memory channel while maintaining a 1.2-GHz data rate - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 19
to 32 devices, imposing an upper limit on memory capacity supported by a single bus. Use of repeater chips enables ProLiant server for which they are designated. Therefore, they prevent improper mixing of single-rank and dual-rank DIMMs. HP memory option kits are listed in each server's user guide - HP ProLiant SL170s | Memory technology evolution: an overview of system memory t - Page 20
Memory Protection Fully-Buffered DIMM technology in HP ProLiant servers Web address http://www.jedec.org http://h18004.www1.hp.com/products/servers/technology/whitepapers/advtechnology.html#mem http://h18004.www1.hp.com/products/servers/technology/whitepapers/advtechnology.html#mem Call to
Memory technology evolution: an overview
of system memory technologies
technology brief, 8
th
edition
Abstract
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2
Introduction
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2
Basic DRAM operation
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2
DRAM storage density and power consumption
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4
Memory access time
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4
Chipsets and system bus timing
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4
Memory bus speed
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5
Burst mode access
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5
SDRAM technology
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6
Bank interleaving
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7
Increased bandwidth
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7
Registered SDRAM modules
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7
DIMM Configurations
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8
Single-sided and double-sided DIMMs
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8
Single-rank, dual-rank, and quad-rank DIMMs
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8
Rank interleaving
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9
Memory channel interleaving
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10
Advanced memory technologies
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11
Double Data Rate SDRAM technologies
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11
DDR-1
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11
DDR-2
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13
DDR-3
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14
Module naming convention and peak bandwidth
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14
Fully-Buffered DIMMs
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15
FB-DIMM architecture
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16
Challenges
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17
Rambus DRAM
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18
Importance of using HP-certified memory modules in ProLiant servers
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19
Conclusion
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19
For more information
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20
Call to action
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20