HP Visualize J210XC Overview of the Visualize fx graphics

HP Visualize J210XC - Workstation Manual

HP Visualize J210XC manual content summary:

  • HP Visualize J210XC | Overview of the Visualize fx graphics - Page 1
    and also the one with the highest performance in the product line. The VISUALIZE fx4 and the VISUALIZE fx2 products use subsets of the chips used in the fx6. The fx6 and fx4 subsystems have support for the optional hardware-accelerated texture map module, which contains a local texture cache
  • HP Visualize J210XC | Overview of the Visualize fx graphics - Page 2
    Figure 1 A chip-level diagram of the VISUALIZE fx6 product. Geometry Accelerator Up to 8 200 MHz/ 33 and Concentration • 2D and 3D Data Path Arbitration • 2D Acceleration • YUV to RGB Conversion Support • Pixel Level Pan and Zoom • Pixel Level Image Rotations Raster Chip • Fragment Processing •
  • HP Visualize J210XC | Overview of the Visualize fx graphics - Page 3
    it in the VISUALIZE fx graphics hardware. We found that the data sets many graphics workstation customers are trying to visualize are very an automobile, a tremendous performance increase can be realized by using the HP occlusion culling technology. To date, several ISVs have begun using occlusion
  • HP Visualize J210XC | Overview of the Visualize fx graphics - Page 4
    primitives to look smaller the further away from the eye they are H Setup calculations for rasterization in the raster chip. There were some interesting problems to solve in the design of the distribution and coalescing of work up and down the geometry chip daisy chain. For example, load balancing
  • HP Visualize J210XC | Overview of the Visualize fx graphics - Page 5
    can be prohibitively slow, various workstation graphics vendors have provided hardware-accelerated 1 A 3D textured skull. The VISUALIZE fx4 and fx6 subsystems support a texture map acceleration option. Pictured the HP-UX operating system to support graphics interrupts, onboard firmware support for
  • HP Visualize J210XC | Overview of the Visualize fx graphics - Page 6
    made these products very appealing systems for texturing applications on workstation graphics. The texture mapping performance on these systems is very competitive. The VISUALIZE fx6 texture fill rate is about twice that of the VISUALIZE fx4 texture option. However, fill rates alone do not describe
  • HP Visualize J210XC | Overview of the Visualize fx graphics - Page 7
    the stencil buffer,* and an alpha buffer** on the VISUALIZE fx6. To accomplish its work the raster chip performs four spec.org/gpc Acknowledgments We would like to thank Paul Martz for the shadow texture image (Figure 2 on page 33). Noel D. Scott Noel Scott is a senior engineer at the HP Workstation
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28
May 1998
The Hewlett-Packard Journal
Article 4
1998 Hewlett Packard Company
An Overview of the VISUALIZE fx Graphics
Accelerator Hardware
Three graphics accelerator products with different levels of performance are
based on varying combinations of five custom integrated circuits. In addition,
these products are the first ones from Hewlett-Packard to provide native
acceleration for the OpenGL
API.
T
he VISUALIZE fx family of graphics subsystems consists of three
products, fx
6
, fx
4
, and fx
2
, and an optional hardware texture mapping module.
These products are built around a common architecture using the same
custom integrated circuits. The primary difference between these controllers
is the number of custom chips used in each product (see
Table I)
.
Table I
Number of custom chips in the different
VISUALIZE fx products
Product
Texture
Chip
Geometry
Chip
Raster
Chip
fx
2
1
2
fx
4
1
2
2
fx
6
2
3
4
A chip-level block diagram of the VISUALIZE fx
6
product is shown in
Figure 1
.
This is the most complex configuration and also the one with the highest
performance in the product line. The VISUALIZE fx
4
and the VISUALIZE fx
2
products use subsets of the chips used in the fx
6
. The fx
6
and fx
4
subsystems
have support for the optional hardware-accelerated texture map module,
which contains a local texture cache for storage of texture map images. If the
texture accelerator is not present, the bus between the interface chip and the
first raster chip is directly connected.
Noel D. Scott
Daniel M. Olsen
Ethan W. Gannett