Intel 925 Data Sheet - Page 111

PCI Express*-Graphics Sequence Status, PCI Express*-Graphics Legacy Control

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Host-PCI Express* Graphics Bridge Registers (D1:F0) R Address Offset BA-BBh BC-BDh BE-BFh C0-C3h C4-EBh EC-EFh F0-FFh 100-103h 104-107h 108-10Bh 10C-10Dh 10E-10Fh 110-113h 114-117h 118-119h 11A-11Bh 11C-11Fh 120-123h 124-125h 126-127h 128-13Fh 140-143h 144-147h 148-14Fh 150-153h 154-157h 158-15Fh 160-217h 218-21Fh 220-FFFh Register Symbol SLOTSTS RCTL - RSTS - PEGLC - VCECH PVCCAP1 PVCCAP2 PVCCTL - VC0RCAP VC0RCTL - VC0RSTS VC1RCAP VC1RCTL - VC1RSTS - RCLDECH ESD - LE1D - LE1A - PEGSSTS - Register Name Slot Status Root Control Reserved Root Status Reserved PCI Express*-Graphics Legacy Control Reserved Virtual Channel Enhanced Capability Header Port VC Capability Register 1 Port VC Capability Register 2 Port VC Control Reserved VC0 Resource Capability VC0 Resource Control Reserved VC0 Resource Status VC1 Resource Capability VC1 Resource Control Reserved VC1 Resource Status Reserved Root Complex Link Declaration Enhanced Capability Header Element Self Description Reserved Link Entry 1 Description Reserved Link Entry 1 Address Reserved PCI Express*-Graphics Sequence Status Reserved Default Value 0X00h 0000h - 00000000h - 00000000h - 14010002h 00000001h 00000001h 0000h - 00000000h 8000007Fh - 0000h 00008000h 01000000h - 0000h - 00010005h 02000100h - 00000000h - 0000000000 000000h - 0000000000 000FFFh - Access RO, R/W/C R/W - RO, R/W/C - R/W, RO - RO RO, R/WO RO R/W - RO RO, R/W - RO RO RO, R/W - RO - RO RO, R/WO - RO, R/WO - R/WO - RO - Intel® 82925X/82925XE MCH Datasheet 111

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Host-PCI Express* Graphics Bridge Registers (D1:F0)
R
Intel
®
82925X/82925XE MCH Datasheet
111
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
BA–BBh
SLOTSTS
Slot Status
0X00h
RO, R/W/C
BC–BDh
RCTL
Root Control
0000h
R/W
BE–BFh
—
Reserved
—
—
C0–C3h
RSTS
Root Status
00000000h
RO, R/W/C
C4–EBh
—
Reserved
—
—
EC–EFh
PEGLC
PCI Express*-Graphics Legacy Control
00000000h
R/W, RO
F0–FFh
—
Reserved
—
—
100–103h
VCECH
Virtual Channel Enhanced Capability
Header
14010002h
RO
104–107h
PVCCAP1
Port VC Capability Register 1
00000001h
RO, R/WO
108–10Bh
PVCCAP2
Port VC Capability Register 2
00000001h
RO
10C–10Dh
PVCCTL
Port VC Control
0000h
R/W
10E–10Fh
—
Reserved
—
—
110–113h
VC0RCAP
VC0 Resource Capability
00000000h
RO
114–117h
VC0RCTL
VC0 Resource Control
8000007Fh
RO, R/W
118–119h
—
Reserved
—
—
11A–11Bh
VC0RSTS
VC0 Resource Status
0000h
RO
11C–11Fh
VC1RCAP
VC1 Resource Capability
00008000h
RO
120–123h
VC1RCTL
VC1 Resource Control
01000000h
RO, R/W
124–125h
—
Reserved
—
—
126–127h
VC1RSTS
VC1 Resource Status
0000h
RO
128–13Fh
—
Reserved
—
—
140–143h
RCLDECH
Root Complex Link Declaration
Enhanced Capability Header
00010005h
RO
144–147h
ESD
Element Self Description
02000100h
RO, R/WO
148–14Fh
—
Reserved
—
—
150–153h
LE1D
Link Entry 1 Description
00000000h
RO, R/WO
154–157h
—
Reserved
—
—
158–15Fh
LE1A
Link Entry 1 Address
0000000000
000000h
R/WO
160–217h
—
Reserved
—
—
218–21Fh
PEGSSTS
PCI Express*-Graphics Sequence Status
0000000000
000FFFh
RO
220–FFFh
—
Reserved
—
—