Intel 925 Data Sheet - Page 12
Intel, 82925X/82925XE MCH Features - driver
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R Intel® 82925X/82925XE MCH Features Processor Interface System Memory ⎯ One Intel® Pentium® 4 processor (supports ⎯ One or two 64-bit wide DDR2 SDRAM 775-land package) data channels ⎯ Supports Pentium 4 processor FSB interrupt ⎯ Bandwidth up to 8.5 GB/s (DDR2 533) in delivery dual-channel Interleaved mode ⎯ 800 MT/s (200 MHz) FSB ⎯ ECC (82925X MCH Only) and Non-ECC ⎯ 1066 MT/s (266 MHz) FSB (82925XE memory MCH Only) ⎯ 256-Mb, 512-Mb and 1-Gb DDR2 ⎯ Supports Hyper-Threading Technology technologies (HT Technology)Ω ⎯ Only x8, x16, DDR2 devices with four ⎯ FSB Dynamic Bus Inversion (DBI) banks and also supports eight bank, 1-Gbit ⎯ 32-bit host bus addressing for access to DDR2 devices. 4 GB of memory space ⎯ Opportunistic refresh ⎯ 12-deep In-Order Queue ⎯ Up to 64 simultaneously open pages (four ⎯ 1-deep Defer Queue ranks of eight bank devices* 2 channels) ⎯ GTL+ bus driver with integrated GTL ⎯ SPD (Serial Presence Detect) scheme for termination resistors DIMM detection support ⎯ Supports a Cache Line Size of 64 bytes ⎯ Suspend-to-RAM support using CKE ⎯ Supports Intel Pentium® 4 processors with ⎯ Supports configurations defined in the Intel® EM64T Φ JEDEC DDR2 DIMM specification only DMI Interface PCI Express Graphics Interface ⎯ A chip-to-chip connection interface to Intel® ⎯ One x16 PCI Express port ICH6 ⎯ Compatible with the PCI Express Base ⎯ 2 GB/s point-to-point DMI to ICH6 (1 GB/s Specification Revision 1.0a each direction) Package ⎯ 100 MHz reference clock (shared with PCI ⎯ 37.5 mm × 37.5 mm., 1210 balls, variable Express Graphics Attach). ball pitch ⎯ 32-bit downstream addressing ⎯ Messaging and Error Handling 12 Intel® 82925X/82925XE MCH Datasheet