Intel 925 Data Sheet - Page 122

Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.16 MLIMIT1-Memory Limit Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 22h 0000h R/W 16 bits This register controls the processor-to-PCI Express Graphics non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read. Configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note: Memory range covered by MBASE and MLIMIT registers are used to map non-pre-fetchable PCI Express Graphics address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map pre-fetchable address ranges (typically, graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved processor-PCI Express memory access performance. Note: Configuration software is responsible for programming all address range registers (pre-fetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other and/or with the ranges covered with the main memory). There is no provision in the MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. Bit Access & Default Description 15:4 R/W Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the 000h upper limit of the address range passed to PCI Express*. 3:0 Reserved 122 Intel® 82925X/82925XE MCH Datasheet