Intel 925 Data Sheet - Page 128
PM_CAPID1-Power Management Capabilities D1:F0, PCI Device, Address Offset, Default Value
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Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.23 PM_CAPID1-Power Management Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 80h 1902 9001h or 1902 A001h RO 32 bits Bit 31:27 26 25 24:22 21 20 19 18:16 15:8 7:0 Access & Default RO 19h RO 0b RO 0b RO 000b RO 0 b RO 0b RO 0b RO 010b RO 90h or A0h RO 01h Description PME Support: This field indicates the power states in which this device may indicate PME wake via PCI Express messaging. D0, D3hot, and D3cold. This device is not required to do anything to support D3hot and D3cold; it simply must report that those states are supported. Refer to the PCI Power Management 1.1 specification for encoding explanation and other power management details. D2: Hardwired to 0 to indicate that the D2 power management state is NOT supported. D1: Hardwired to 0 to indicate that the D1 power management state is NOT supported. Auxiliary Current: Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary current requirements. Device Specific Initialization (DSI): Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it. Auxiliary Power Source (APS): Hardwired to 0. PME Clock: Hardwired to 0 to indicate this device does NOT support PME# generation. PCI PM CAP Version: Hardwired to 02h to indicate there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the PCI Power Management Interface Specification. Pointer to Next Capability: This field contains a pointer to the next item in the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the capabilities list is the Message Signaled Interrupts (MSI) capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next item in the capabilities list is the PCI Express* capability at A0h. Capability ID: Value of 01h identifies this linked list item (capability structure) as being for PCI Power Management registers. 128 Intel® 82925X/82925XE MCH Datasheet