Intel 925 Data Sheet - Page 148
PVCCAP2-Port VC Capability Register 2 D1:F0, PVCCTL-Port VC Control D1:F0
UPC - 683728067724
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Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.47 PVCCAP2-Port VC Capability Register 2 (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 108h 00000001h RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit 31:24 23:8 7:0 Access & Default Description RO VC Arbitration Table Offset: This field indicates the location of the VC Arbitration 00h Table. This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the Virtual Channel Capability Structure. A value of 0 indicates that the table is not present (due to fixed VC priority). Reserved RO VC Arbitration Capability: This field indicates that the only possible VC 01h arbitration scheme is hardware fixed (in the root complex). VC1 is the highest priority, VC0 is the lowest priority. 8.1.48 PVCCTL-Port VC Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 10Ch 0000h R/W 16 bits Bit Access & Default Description 15:4 Reserved 3:1 R/W VC Arbitration Select: This field will be programmed by software to the only 000b possible value as indicated in the VC Arbitration Capability field. The value 001b when written to this field will indicate the VC arbitration scheme is hardware fixed (in the root complex). This field can not be modified when more than one VC in the LPVC group is enabled. 0 Reserved 148 Intel® 82925X/82925XE MCH Datasheet