Intel 925 Data Sheet - Page 151

VC1RCTL-VC1 Resource Control D1:F0

Page 151 highlights

Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.53 VC1RCTL-VC1 Resource Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 120h 01000000h RO, R/W 32 bits Controls the resources associated with PCI Express Virtual Channel 1. Bit 31 30:27 26:24 23:8 7:1 0 Access & Default Description R/W 0b R/W 001b R/W 00h RO 0b VC1 Enable 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions in note below. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read from this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is completed for the PCI Express* port); a 0 read from this bit indicates that the Virtual Channel is currently disabled. Notes: • To enable a Virtual Channel, the VC Enable bits for that Virtual Channel must be set in both Components on a Link. • To disable a Virtual Channel, the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link. • Software must ensure that no traffic is using a Virtual Channel at the time it is disabled. • Software must fully disable a Virtual Channel in both Components on a Link before re-enabling the Virtual Channel. Reserved VC1 ID: Assigns a VC ID to the VC resource. Assigned value must be non-zero. This field cannot be modified when the VC is already enabled. Reserved TC/VC1 Map: This field indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. TC0/VC1 Map: Traffic Class 0 is always routed to VC0. Intel® 82925X/82925XE MCH Datasheet 151

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
  • 189
  • 190
  • 191
  • 192
  • 193
  • 194
  • 195
  • 196
  • 197
  • 198
  • 199
  • 200
  • 201
  • 202
  • 203
  • 204
  • 205
  • 206
  • 207
  • 208
  • 209
  • 210
  • 211
  • 212
  • 213
  • 214
  • 215
  • 216
  • 217
  • 218
  • 219
  • 220
  • 221
  • 222
  • 223
  • 224
  • 225
  • 226
  • 227
  • 228
  • 229
  • 230
  • 231
  • 232
  • 233
  • 234
  • 235
  • 236
  • 237
  • 238
  • 239
  • 240
  • 241
  • 242

Host-PCI Express* Graphics Bridge Registers (D1:F0)
R
Intel
®
82925X/82925XE MCH Datasheet
151
8.1.53
VC1RCTL—VC1 Resource Control (D1:F0)
PCI Device:
1
Address Offset:
120h
Default Value:
01000000h
Access:
RO, R/W
Size:
32 bits
Controls the resources associated with PCI Express Virtual Channel 1.
Bit
Access &
Default
Description
31
R/W
0b
VC1 Enable
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled. See exceptions in note below.
Software must use the VC Negotiation Pending bit to check whether the VC
negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read
from this VC Enable bit indicates that the VC is enabled (Flow Control
Initialization is completed for the PCI Express* port); a 0 read from this bit
indicates that the Virtual Channel is currently disabled.
Notes:
To enable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be set in both Components on a Link.
To disable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be cleared in both Components on a Link.
Software must ensure that no traffic is using a Virtual Channel at the time it is
disabled.
Software must fully disable a Virtual Channel in both Components on a Link
before re-enabling the Virtual Channel.
30:27
Reserved
26:24
R/W
001b
VC1 ID:
Assigns a VC ID to the VC resource. Assigned value must be non-zero.
This field cannot be modified when the VC is already enabled.
23:8
Reserved
7:1
R/W
00h
TC/VC1 Map:
This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource. In order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding transactions with
the TC labels are targeted at the given Link.
0
RO
0b
TC0/VC1 Map:
Traffic Class 0 is always routed to VC0.