Intel 925 Data Sheet - Page 153

Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.56 ESD-Element Self Description (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 144h 02000100h RO, R/WO 32 bits This register provides information about the root complex element containing this Link Declaration Capability. Bit 31:24 23:16 15:8 7:4 3:0 Access & Default Description RO 02h R/WO 00h RO 01h RO 0h Port Number: This field specifies the port number associated with this element with respect to the component that contains this element. The egress port of the component to provide arbitration to this Root Complex Element uses this port number value. Component ID: This field indicates the physical component that contains this Root Complex Element. Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored. Number of Link Entries: This field indicates the number of link entries following the Element Self Description. This field reports 1 (to Egress port only as peer-topeer capabilities in this topology are not reported). Reserved Element Type: This field indicates the type of the Root Complex Element. 0h = root port. Intel® 82925X/82925XE MCH Datasheet 153