Intel 925 Data Sheet - Page 154

Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.57 LE1D-Link Entry 1 Description (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 150h 00000000h RO, R/WO 32 bits This register provides the First part of a Link Entry that declares an internal link to another Root Complex Element. Bit 31:24 23:16 15:2 1 0 Access & Default Description RO 00h R/WO 00h RO 0b R/WO 0b Target Port Number: This field specifies the port number associated with the element targeted by this link entry (Egress Port). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID: This field indicates the physical or logical component that is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored. Reserved Link Type: This field indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of the target RCRB. Link Valid: 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link. 154 Intel® 82925X/82925XE MCH Datasheet