Intel 925 Data Sheet - Page 17
System Memory Interface - 925x
UPC - 683728067724
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Introduction R 1.3.2 System Memory Interface The MCH integrates a system memory DDR2 controller with two, 64-bit wide interfaces. Only Double Data Rate (DDR2) memory is supported; consequently, the buffers support only SSTL_1.8 V signal interfaces. The memory controller interface is fully configurable through a set of control registers. Features of the MCH memory controller include: • The MCH System Memory Controller directly supports one or two channels of memory (each channel consisting of 64 data lines). • Supports two memory addressing organization options: ⎯ The memory channels are asymmetric: "Stacked" channels are assigned addresses serially. Channel B addresses are assigned after all Channel A addresses. ⎯ The memory channels are interleaved: Addresses are ping-ponged between the channels after each cache line (64-B boundary). • Available bandwidth up to: ⎯ 3.2 GB/s (DDR2 400) for single-channel mode ⎯ 6.4 GB/s in dual-channel interleaved mode assuming DDR2 400 MHz. ⎯ 8.5 GB/s in dual-channel interleaved mode assuming DDR2 533 MHz. • Supports DDR2 memory DIMM frequencies of 400 MHz and 533 MHz. The speed used in all channels is the speed of the slowest DIMM in the system. • I/O Voltage of 1.8 V for DDR2. • I/O Voltage of 1.9 V for DDR2 533 MHz CL3-3-3. • Supports non-ECC and ECC (925X only) memory. • Supports 256-Mb, 512-Mb and 1-Gb DDR2 technologies • Supports only x8, x16, DDR2 devices with four banks and also supports eight bank, 1-Gbit DDR2 devices. • Supports opportunistic refresh • In dual channel mode the MCH supports 64 simultaneously open pages (four ranks of eight bank devices* 2 channels) • Supports Partial Writes to memory using Data Mask (DM) signals. • Supports page sizes of 4 KB, 8 KB, and 16 KB. • Supports a burst length of 8 for single-channel and dual-channel interleaved and asymmetric operating modes. • Supports unbuffered DIMMs. • SPD (Serial Presence Detect) scheme for DIMM detection support • Suspend-to-RAM support using CKE • Supports configurations defined in the JEDEC DDR2 DIMM specification only The MCH supports a memory thermal management scheme to selectively manage reads and/or writes. Memory thermal management can be triggered either by on-die thermal sensor, or by preset limits. Management limits are determined by weighted sum of various commands that are scheduled on the memory interface. Intel® 82925X/82925XE MCH Datasheet 17