Intel 925 Data Sheet - Page 171

System Address Map R 9.4.10 9.4.11 9.4.12 The I/O accesses (other than ones used for configuration space access) are forwarded normally to the DMI bus unless they fall within the PCI Express I/O address range as defined by the mechanisms explained below. I/O writes are not posted. Memory writes to the ICH6 or PCI Express are posted. The MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status. Upstream I/O cycles and configuration cycles should never occur. If one does occur, the request will route as a read to memory address 0h so a completion is naturally generated (whether the original request was a read or write). The transaction will complete with a UR completion status. For Pentium 4 processors, I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from the processor as 1 transaction. The MCH will break this into 2 separate transactions. This has not been done on previous chipsets. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed to be split into 2 transactions by the processor. PCI Express* I/O Address Mapping The MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus interface when processor-initiated I/O cycle addresses are within the PCI Express I/O address range. MCH Decode Rules and Cross-Bridge Address Mapping The following are MCH decode rules and cross-bridge address mapping used in this chipset: • VGAA = 000A_0000h - 000A_FFFFh • MDA = 000B_0000h - 000B_7FFFh • VGAB = 000B_8000h - 000B_FFFFh • MAINMEM = 0100_0000h to TOLUD Legacy VGA and I/O Range Decode Rules The legacy 128-KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to PCI Express (Device 1), and/or to the DMI depending on BIOS programming. Priority for VGA mapping is constant in that the MCH always decodes internally mapped devices first. The MCH always positively decodes internally mapped devices, namely the PCI Express. § Intel® 82925X/82925XE MCH Datasheet 171