Intel 925 Data Sheet - Page 181

Functional Description R 10.3.2 10.3.3 10.3.4 10.3.5 DRAM Clock Generation The MCH generates three differential clock pairs for every supported DIMM. There are a total of 6 clock pairs driven directly by the MCH to 2 DIMMs per channel. Suspend to RAM and Resume When entering the Suspend-to-RAM (STR) state, the SDRAM controller will flush pending cycles and then enter all SDRAM rows into self refresh. In STR, the CKE signals remain LOW so the SDRAM devices will perform self-refresh. DDR2 On-Die Termination On-die termination (ODT) is a feature that allows a DRAM to turn on/off internal termination resistance for each DQ, DM, DQS, and DQS# signal for x8 and x16 configurations via the ODT control signals. The ODT feature is designed to improve signal integrity of the memory channel by allowing the termination resistance for the DQ, DM, DQS, and DQS# signals to be located inside the DRAM devices themselves, instead of on the motherboard. The MCH drives out the required ODT signals, based on memory configuration and which rank is being written to or read from, to the DRAM devices on a targeted DIMM rank to enable or disable their termination resistance. DDR2 Off-Chip Driver Impedance Calibration The OCD impedance adjustment mode allows the MCH to measure and adjust the pull-up and pull-down strength of the DRAM devices. It uses a series of EMRS commands to guide the DRAM through measurement and calibration cycles. This feature is described in more detail in the JEDEC DDR2 device specification. The algorithm and sequence of the adjustment cycles is handled by software. The MCH adjusts the DRAM driver impedance by issuing OCD commands to the DIMM and looking at the analog voltage on the DQ lines. Intel® 82925X/82925XE MCH Datasheet 181