Intel 925 Data Sheet - Page 191

Symbol, Signal, Group, Parameter, Notes

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Electrical Characteristics R Symbol VCROSS VOL VOH IOL IOH VIL VIH ILEAK CIN VIL VIH ILEAK CIN Signal Group Parameter Min Nom Max Unit Notes3 (o) Crossing Voltage (p) Output Low Voltage (CMOS Outputs) (p) Output High Voltage (CMOS Outputs) (p) Output Low Current (CMOS Outputs) (p) Output High Current (CMOS Outputs) (p) Input Low Voltage (p) Input High Voltage (p) Crossing Voltage (p) Input Capacitance (n1) Input Low Voltage (n1) Input High Voltage (n1) Crossing Voltage (n1) Input Capacitance 0.45 x (VIH - VIL) - 2.1 - -1 - 1.4 - 3.0 - 2.0 - 4.690 0.5 x (VIH - VIL) - - - - - - - - - - - 0.55 x (VIH - VIL) 0.4 - 1 - 1.1 ±10 6.0 0.8 - ±100 5.370 V V V mA @VOL_HI max mA @VOH_HI min V V µA pF V V µA 0 < Vin < VCC3_3 pF NOTES: 1. Determined with 2x MCH DDR2 Buffer Strength Settings into a 50 Ω to 0.5xVCCSM (DDR2) test load. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter compliance eye diagram of the PCI Express Interface Specification 1.0a and measured over any 250 consecutive TX Uls. 3. Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown in Receiver compliance eye diagram of the PCI Express Interface Specification 1.0a should be used as the RX device when taking measurements. § Intel® 82925X/82925XE MCH Datasheet 191

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Electrical Characteristics
R
Intel
®
82925X/82925XE MCH Datasheet
191
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
3
V
CROSS
(o)
Crossing Voltage
0.45 x
(V
IH
– V
IL
)
0.5 x
(V
IH
– V
IL
)
0.55 x
(V
IH
– V
IL
)
V
V
OL
(p)
Output Low Voltage
(CMOS Outputs)
—
—
0.4
V
V
OH
(p)
Output High Voltage
(CMOS Outputs)
2.1
—
—
V
I
OL
(p)
Output Low Current
(CMOS Outputs)
—
—
1
mA
@V
OL_HI
max
I
OH
(p)
Output High Current
(CMOS Outputs)
–1
—
—
mA
@V
OH_HI
min
V
IL
(p)
Input Low Voltage
—
—
1.1
V
V
IH
(p)
Input High Voltage
1.4
V
I
LEAK
(p)
Crossing Voltage
—
—
±
10
µ
A
C
IN
(p)
Input Capacitance
3.0
—
6.0
pF
V
IL
(n1)
Input Low Voltage
—
—
0.8
V
V
IH
(n1)
Input High Voltage
2.0
—
—
V
I
LEAK
(n1)
Crossing Voltage
—
—
±
100
µ
A
0 < V
in
< VCC3_3
C
IN
(n1)
Input Capacitance
4.690
—
5.370
pF
NOTES:
1.
Determined with 2x MCH DDR2 Buffer Strength Settings into a 50
Ω
to 0.5xV
CCSM
(DDR2) test load.
2.
Specified at the measurement point into a timing and voltage compliance test load as shown in
Transmitter compliance eye diagram of the
PCI Express Interface Specification 1.0a
and measured over
any 250 consecutive TX Uls.
3.
Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown
in Receiver compliance eye diagram of the
PCI Express Interface Specification 1.0a
should be used as
the RX device when taking measurements.
§