Intel 925 Data Sheet - Page 20

Introduction R 1.3.6 1.3.7 MCH Clocking The differential FSB clock (HCLKP/HCLKN) is set to 200 MHz on the 82925X MCH and 266 MHz on the 82925XE MCH. This supports FSB transfer rates of 800 MT/s for the 82925X MCH and FSB transfer rates of 1066 MT/s for the 82925XE MCH. The Host PLL generates 2X, 4X, and 8X versions of the host clock for internal optimizations. The MCH core clock is synchronized to the host clock. The internal and external memory clocks of 133 MHz, 200 MHz, and 266 MHz are generated from one of two MCH PLLs that use the host clock as a reference. This includes 2X and 4X for internal optimizations. The PCI Express core clock of 250 MHz is generated from a separate PCI Express PLL. This clock uses the fixed 100 MHz Serial Reference Clock (GCLKP/GCLKN) for reference. All of the above mentioned clocks are capable of tolerating Spread Spectrum clocking as defined in the Clock Generator specification. Host, Memory, and PCI Express* x16 Graphics PLLs, and all associated internal clocks are disabled until PWROK is asserted. Power Management MCH Power Management support includes: • PC99 suspend to DRAM support ("STR", mapped to ACPI state S3) • SMRAM space remapping to A0000h (128 KB) • Supports extended SMRAM space above 256 MB, additional 1-MB TSEG from the Base of graphics stolen memory (BSM) when enabled, and cacheable (cacheability controlled by processor) • ACPI Rev 1.0 compatible power management • Supports processor states: C0, C1, C2, C3, and C4 • Supports System states: S0, S1, S3, S4, and S5 • Supports processor Thermal Management 2 (TM2) • Microsoft Windows NT* Hardware Design Guide v1.0 compliant § 20 Intel® 82925X/82925XE MCH Datasheet