Intel 925 Data Sheet - Page 23
Host Interface Signals, Address Strobe, Block Next Request, Priority Agent Bus Request, Bus Request 0 - cpu
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Signal Description R 2.1 Host Interface Signals Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination voltage of the Host Bus (VTT). Signal Name HADS# HBNR# HBPRI# HBREQ0# HCPURST# HDBSY# HDEFER# HDINV[3:0]# Type I/O GTL+ I/O GTL+ O GTL+ I/O GTL+ O GTL+ I/O GTL+ O GTL+ I/O GTL+ Description Address Strobe: The processor bus owner asserts HADS# to indicate the first of two cycles of a request phase. The MCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: This signal is used to block the current request bus owner from issuing new requests. This signal is used to dynamically control the processor bus pipeline depth. Priority Agent Bus Request: The MCH is the only Priority Agent on the processor bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0: The MCH pulls the processor's bus HBREQ0# signal low during HCPURST#. The processor samples this signal on the active-toinactive transition of HCPURST#. The minimum setup time for this signal is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. HBREQ0# should be tri-stated after the hold time requirement has been satisfied. CPU Reset: The HCPURST# pin is an output from the MCH. The MCH asserts HCPURST# while RSTIN# is asserted and for approximately 1 ms after RSTIN# is de-asserted. The HCPURST# allows the processors to begin execution in a known state. Note that the Intel® ICH6 must provide processor frequency select strap setup and hold times around HCPURST#. This requires strict synchronization between MCH HCPURST# de-assertion and the Intel® ICH6 driving the straps. Data Bus Busy: This signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: Signals that the MCH will terminate the transaction currently being snooped with either a deferred response or with a retry response. Dynamic Bus Inversion: Driven along with the HD[63:0] signals. Indicates if the associated signals are inverted or not. HDINV[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16 bit group never exceeds 8. HDINVx# Data Bits HDINV3# HD[63:48] HDINV2# HD[47:32] HDINV1# HD[31:16] HDINV0# HD[15:0] Intel® 82925X/82925XE MCH Datasheet 23