Intel 925 Data Sheet - Page 24
Signal Description, Intel, 82925X/82925XE MCH Datasheet, Signal Name, Description
UPC - 683728067724
View all Intel 925 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 24 highlights
Signal Description R Signal Name HDRDY# HEDRDY# HA[31:3]# HADSTB[1:0]# HD[63:0] HDSTBP[3:0]# HDSTBN[3:0]# HHIT# HHITM# HLOCK# HPCREQ# Type I/O GTL+ O GTL+ I/O GTL+ I/O GTL+ I/O GTL+ I/O GTL+ I/O GTL+ I/O GTL+ I/O GTL+ I GTL+ 2x Description Data Ready: This signal is asserted for each cycle that data is transferred. Early Data Ready: This signal indicates that the data phase of a read transaction will start on the bus exactly one common clock after assertion. Host Address Bus: HA[31:3]# connect to the processor address bus. During processor cycles, the HA[31:3]# are inputs. The MCH drives HA[31:3]# during snoop cycles on behalf of DMI and PCI Express Graphics initiators. HA[31:3]# are transferred at 2x rate. Host Address Strobe: The source synchronous strobes used to transfer HA[31:3]# and HREQ[4:0] at the 2x transfer rate. Host Data: These signals are connected to the processor data bus. Data on HD[63:0] is transferred at 4x rate. Note that the data signals may be inverted on the processor bus, depending on the HDINV[3:0]# signals. Differential Host Data Strobes: The differential source synchronous strobes are used to transfer HD[63:0]# and HDINV[3:0]# at 4x transfer rate. These signals are named this way because they are not level sensitive. Data is captured on the falling edge of both strobes. Hence, they are pseudo-differential, and not true differential. Strobes Data Bits HDSTBP3#, HDSTBN3# HD[63:48] HDINV3# HDSTBP2#, HDSTBN2# HD[47:32] HDINV2# HDSTBP1#, HDSTBN1# HD[31:16] HDINV1# HDSTBP0#, HDSTBN0# HD[15:0] HDINV0# Hit: This signal indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with HHITM# by the target to extend the snoop window. Hit Modified: This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. This signal is also driven in conjunction with HHIT# to extend the snoop window. Host Lock: All processor bus cycles sampled with the assertion of HLOCK# and HADS#, until the negation of HLOCK# must be atomic (i.e., no DMI or PCI Express Graphics accesses to DRAM are allowed when HLOCK# is asserted by the processor). Precharge Request: The processor provides a "hint" to the MCH that it is OK to close the DRAM page of the memory read request with which the hint is associated. The MCH uses this information to schedule the read request to memory using the special "AutoPrecharge" attribute. This causes the DRAM to immediately close (Precharge) the page after the read data has been returned. This allows subsequent processor requests to more quickly access information on other DRAM pages, since it will no longer be necessary to close an open page prior to opening the proper page. Asserted by the requesting agent during both halves of Request Phase. The same information is provided in both halves of the request phase. 24 Intel® 82925X/82925XE MCH Datasheet