Intel 925 Data Sheet - Page 26

Signal Description R 2.2 26 DDR2 DRAM Channel A Interface Signal Name SCLK_A[5:0] SCLK_A[5:0]# SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SCB_A[7:0] (Intel® 82925X Only) SDQS_A[8:0] (82925X MCH) SDQS_A[7:0] (82925XE MCH) SDQS_A[8:0]# (82925X MCH) SDQS_A[7:0]# (82925XE MCH) SCKE_A[3:0] SODT_A[3:0] Type O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 I/O SSTL-1.8 2x O SSTL-1.8 2X I/O SSTL-1.8 2X I/O SSTL-1.8 2x Description SDRAM Differential Clock: (3 per DIMM). SCLK_Ax and its complement SCLK_Ax# signal make a differential clock pair output. The crossing of the positive edge of SCLK_Ax and the negative edge of its complement SCLK_Ax# are used to sample the command and control signals on the SDRAM. SDRAM Complementary Differential Clock: (3 per DIMM) These are the complementary differential DDR2 Clock signals. Chip Select: (1 per Rank) These signals select particular SDRAM components during the active state. There is one chip select for each SDRAM rank. Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM Bank Select: These signals define which banks are selected within each SDRAM rank DDR2: 1-Gb technology is 8 banks. Row Address Strobe: This signal is used with SCAS_A# and SWE_A# (along with SCS_A#) to define the SDRAM commands. Column Address Strobe: This signal is used with SRAS_A# and SWE_A# (along with SCS_A#) to define the SDRAM commands. Write Enable: This signal is used with SCAS_A# and SRAS_A# (along with SCS_A#) to define the SDRAM commands. Data Lines: SDQ_A signals interface to the SDRAM data bus. Data Mask: When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SDM_Ax signal for every data byte lane. ECC Check Byte: These signals require a 6-layer board to be routed. Data Strobes: For DDR2, SDQS_Ax and its complement SDQS_Ax# signal make up a differential strobe pair. The data is captured at the crossing point of SDQS_Ax and its complement SDQS_Ax# during read and write transactions. I/O SSTL-1.8 2x Data Strobe Complements: These signals are the complementary DDR2 strobe signals. O SSTL-1.8 O SSTL-1.8 Clock Enable: (1 per Rank) SACKE is used to initialize the SDRAMs during power-up, to power-down SDRAM ranks, and to place all SDRAM ranks into and out of self-refresh during Suspend-to-RAM. On Die Termination: Active On-die Termination Control signals for DDR2 devices. Intel® 82925X/82925XE MCH Datasheet