Intel 925 Data Sheet - Page 32
Table 2-2. System Memory Reset and S3 States
UPC - 683728067724
View all Intel 925 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 32 highlights
Signal Description Table 2-2. System Memory Reset and S3 States Interface Signal Name System Memory System Memory Channel A SCLK_A[5:0] SCLK_A[5:0]# SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SCB_A[7:0]1 SDQS_A[8:0] 2 SDQS_A[8:0]# 2 SCKE_A[3:0] SODT_A[3:0] Channel B SCLK_B[5:0] SCLK_B[5:0]# SCS_B[3:0]# SMA_B[13] SMA_B[12:11] SMA_B[10:8] SMA_B[7] SMA_B[6:0] SBS_B[2] SBS_B[1:0] SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] SCB_B[7:0] 1 SDQS_B[8:0] 2 State During I/O RSTIN# Assertion O TRI O TRI O TRI O TRI O TRI O TRI O TRI O TRI I/O TRI O TRI I/O TRI I/O TRI I/O TRI O LV O LV O TRI O TRI O TRI O TRI O LV O TRI O LV O TRI O LV O TRI O TRI O TRI O TRI I/O TRI O TRI I/O TRI I/O TRI State After RSTIN# Deassertion TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI LV LV TRI TRI TRI TRI LV TRI LV TRI LV TRI TRI TRI TRI TRI TRI TRI TRI R S3 Pull-up/ Pull-down TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI LV LV TRI TRI TRI TRI LV TRI LV TRI LV TRI TRI TRI TRI TRI TRI TRI TRI 32 Intel® 82925X/82925XE MCH Datasheet