Intel 925 Data Sheet - Page 46

Host Bridge/DRAM Controller Registers (D0:F0) R Address Offset 52h-53h 54h-57h 58h-5Bh 5Ch 5Dh 5Fh-8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98-9Bh 9Ch 9Dh Register Symbol - DEVEN DEAP DERRSYN DERRDST - PAM0 PAM1 PAM2 PAM3 PAM4 PAM5 PAM6 LAC - TOLUD SMRAM Register Name Reserved Device Enable DRAM Error Address Pointer DRAM Error Syndrome DRAM Error Destination Reserved Programmable Attribute Map 0 Programmable Attribute Map 1 Programmable Attribute Map 2 Programmable Attribute Map 3 Programmable Attribute Map 4 Programmable Attribute Map 5 Programmable Attribute Map 6 Legacy Access Control Reserved Top of Low Usable DRAM System Management RAM Control 9Eh ESMRAMC Extended System Management RAM Control 9F-C7h C8h-C9h - ERRSTS Reserved Error Status CAh-CBh CCh-CDh CEh-CFh D0h-DBh DCh-DFh E0h-E8h ERRCMD SMICMD SCICMD - SKPD CAPID0 Error Command SMI Command SCI Command Reserved Scratchpad Data Capability Identifier E9h-FFh 100h 101h 102h 103h 104h-107h 108h - C0DRB0 C0DRB1 C0DRB2 C0DRB3 - C0DRA0 Reserved Channel A DRAM Rank Boundary Address 0 Channel A DRAM Rank Boundary Address 1 Channel A DRAM Rank Boundary Address 2 Channel A DRAM Rank Boundary Address 3 Reserved Channel A DRAM Rank 0,1 Attribute Default Value - 00000019h 00000000h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h - 08h 00h 00h - 0000h 0000h 0000h 0000h - 00000000h 00000000000 1090009h - 00h 00h 00h 00h - 00h Access - R/W RO/S RO/S RO/S - R/W R/W R/W R/W R/W R/W R/W R/W - R/W RO, R/W/L RO, R/W/L - RO, R/W/L R/W R/W R/W - R/W RO - R/W R/W R/W R/W - R/W 46 Intel® 82925X/82925XE MCH Datasheet