Intel 925 Data Sheet - Page 47
Address, Offset, Register, Symbol, Register Name, Default, Value, Access
UPC - 683728067724
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Host Bridge/DRAM Controller Registers (D0:F0) R Address Offset 109h 10Ah-10Bh 10Ch 10Dh 10E-10F 110h-113h 114h-117h 118h-11Fh 120h-123h 124h-17Fh 180h 181h 182h 183h 184h-187h 188h 189h 18Ah-18Bh 18Ch 18Dh 18Eh-18Fh 190h-193h 194h 195h-19Fh 1A0h-1A3h 1A4h-F0Fh F10h-F13h F14h Register Symbol Register Name C0DRA2 - C0DCLKDIS - C0BNKARC - C0DRT1 - C0DRC0 - C1DRB0 C1DRB1 C1DRB2 C1DRB3 - C1DRA0 C1DRA2 - C1DCLKDIS - C1BNKARC - C1DRT1 - C1DRC0 - PMCFG PMSTS Channel A DRAM Rank 2,3 Attribute Reserved Channel A DRAM Clock Disable Reserved Channel A DRAM Bank Architecture Reserved Channel A DRAM Timing Register Reserved Channel A DRAM Controller Mode 0 Reserved Channel B DRAM Rank Boundary Address 0 Channel B DRAM Rank Boundary Address 1 Channel B DRAM Rank Boundary Address 2 Channel B DRAM Rank Boundary Address 3 Reserved Channel B DRAM Rank 0,1 Attribute Channel B DRAM Rank 2,3 Attribute Reserved Channel B DRAM Clock Disable Reserved Channel B Bank Architecture Reserved Channel B DRAM Timing Register 1 Reserved Channel B DRAM Controller Mode 0 Reserved Power Management Configuration Power Management Status Default Value 00h - 00h - 0000h - 900122h - 00000000h - 00h 00h 00h 00h - 00h 00h - 00h - 0000h - 900122h - 00000000h - 00000000h 00000000h Access R/W - R/W - R/W - R/W - R/W, RO - R/W R/W R/W R/W - R/W R/W - R/W - R/W - R/W, RO - R/W, RO - R/W R/W/C/S Intel® 82925X/82925XE MCH Datasheet 47