Intel 925 Data Sheet - Page 52
MLT-Master Latency Timer D0:F0, HDR-Header Type D0:F0, SVID-Subsystem Vendor Identification D0:F0
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Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.7 4.1.8 4.1.9 MLT-Master Latency Timer (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 0Dh 00h RO 8 bits Device 0 in the MCH is not a PCI master. Therefore this register is not implemented. Bit Access & Default 7:0 Reserved Description HDR-Header Type (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 0Eh 00h RO 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit Access & Default Description 7:0 RO PCI Header (HDR): This field always returns 0 to indicate that the MCH is a 00h single function device with standard header layout. SVID-Subsystem Vendor Identification (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 2Ch 0000h R/WO 16 bits This value is used to identify the vendor of the subsystem. Bit Access & Default Description 15:0 R/WO Subsystem Vendor ID (SUBVID): This field should be programmed during boot- 0000h up to indicate the vendor of the system board. After it has been written once, it becomes read only. 52 Intel® 82925X/82925XE MCH Datasheet