Intel 925 Data Sheet - Page 55
MCHBAR-MCH Memory Mapped Register Range Base, Address D0:F0
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Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.13 MCHBAR-MCH Memory Mapped Register Range Base Address (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 44h 00000000h R/W 32 bits This is the base address for the MCH memory-mapped configuration space. There is no physical memory within this 16-KB window that can be addressed. The 16 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, this register is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset 54h, bit 28] Bit 31:14 13:0 Access & Default R/W 00000h Description MCH Memory Mapped Base Address: This field corresponds to bits 31 to 14 of the base address MCH memory-mapped configuration space. BIOS will program this register resulting in a base address for a 16-KB block of contiguous memory address space. This register ensures that a naturally aligned 16-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the MCH Memory-mapped register set. Reserved Intel® 82925X/82925XE MCH Datasheet 55