Intel 925 Data Sheet - Page 60
DERRSYN-DRAM Error Syndrome D0:F0 Intel
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Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.18 DERRSYN-DRAM Error Syndrome (D0:F0) (Intel® 82925X Only) PCI Device: Address Offset: Default Value: Access: Size: 0 5Ch 00h RO/S 8 bits This register is used to report the ECC syndromes for each quad word of a 32B-aligned data quantity read from the DRAM array. Bit Access & Default Description 7:0 RO/S 00h DRAM ECC Syndrome (DECCSYN): After a DRAM ECC error on any QW of the data chunk resulting from a read command, hardware loads this field with a syndrome that describes the set of bits associated with the first QW containing an error. Note that this field is locked from the time that it is loaded up to the time when the error flag is cleared by software. If the first error was a single bit, correctable error, then a subsequent multiple bit error on any of the QWs in this read transaction or any subsequent read transaction will cause the field to be rerecorded. When a multiple bit error is recorded, the field is locked until the error flag is cleared by software. In all other cases, an error that occurs after the first error, and before the error flag, has been cleared by software, will escape recording. These bits are reset on PWROK. 60 Intel® 82925X/82925XE MCH Datasheet