Intel 925 Data Sheet - Page 67
PAM5-Programmable Attribute Map 5 D0:F0
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Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.25 PAM5-Programmable Attribute Map 5 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 95h 00h R/W 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h0E7FFFh. Bit Access & Default Description 7:6 Reserved 5:4 R/W 0E4000h-0E7FFFh Attribute (HIENABLE): This field controls the steering of read 00b and write cycles that address the BIOS area from 0E4000h to 0E7FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 Reserved 1:0 R/W 0E0000h-0E3FFFh Attribute (LOENABLE): This field controls the steering of read 00b and write cycles that address the BIOS area from 0E0000h to 0E3FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. Intel® 82925X/82925XE MCH Datasheet 67