Intel 925 Data Sheet - Page 82
C0DRB1-Channel A DRAM Rank Boundary Address 1, MCHBAR Registers, Intel, 82925X/82925XE MCH Datasheet
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MCHBAR Registers R 5.1.2 5.1.3 5.1.4 C0DRB1-Channel A DRAM Rank Boundary Address 1 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 101h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRB0. C0DRB2-Channel A DRAM Rank Boundary Address 2 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 102h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRB0. C0DRB3-Channel A DRAM Rank Boundary Address 3 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 103h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRB0. 82 Intel® 82925X/82925XE MCH Datasheet
MCHBAR Registers
R
82
Intel
®
82925X/82925XE MCH Datasheet
5.1.2
C0DRB1—Channel A DRAM Rank Boundary Address 1
MMIO Range:
MCHBAR
Address Offset:
101h
Default Value:
00h
Access:
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.3
C0DRB2—Channel A DRAM Rank Boundary Address 2
MMIO Range:
MCHBAR
Address Offset:
102h
Default Value:
00h
Access:
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.4
C0DRB3—Channel A DRAM Rank Boundary Address 3
MMIO Range:
MCHBAR
Address Offset:
103h
Default Value:
00h
Access:
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.