Intel 925 Data Sheet - Page 85
C0BNKARC-Channel A DRAM Bank Architecture
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MCHBAR Registers R 5.1.8 C0BNKARC-Channel A DRAM Bank Architecture MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 10Eh 0000h R/W 16 bits This register is used to program the bank architecture for each Rank. Bit Access & Default 15:8 Reserved 7:6 R/W Rank 3 Bank Architecture 00b 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved 5:4 R/W Rank 2 Bank Architecture 00b 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved 3:2 R/W Rank 1 Bank Architecture 00b 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved 1:0 R/W Rank 0 Bank Architecture 00b 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved Description Intel® 82925X/82925XE MCH Datasheet 85
MCHBAR Registers
R
Intel
®
82925X/82925XE MCH Datasheet
85
5.1.8
C0BNKARC—Channel A DRAM Bank Architecture
MMIO Range:
MCHBAR
Address Offset:
10Eh
Default Value:
0000h
Access:
R/W
Size:
16 bits
This register is used to program the bank architecture for each Rank.
Bit
Access &
Default
Description
15:8
Reserved
7:6
R/W
00b
Rank 3 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
5:4
R/W
00b
Rank 2 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
3:2
R/W
00b
Rank 1 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
1:0
R/W
00b
Rank 0 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved