Intel 925 Data Sheet - Page 87
MCHBAR Registers, Intel, 82925X/82925XE MCH Datasheet, DRAM RAS to CAS Delay t, DRAM RAS Precharge t
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MCHBAR Registers R Bit Access & Default Description 6:4 R/W DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted 010b between a row activate command and a read or write command to that row. 000 = 2 DRAM clocks 001 = Reserved 010 = 4 DRAM clocks 011 = 5 DRAM clocks 100 - 111 = Reserved 3 Reserved 2:0 R/W DRAM RAS Precharge (tRP). This bit controls the number of clocks that are 010b inserted between a row precharge command and an activate command to the same rank. 000 = 2 DRAM clocks 001 = Reserved 010 = 4 DRAM clocks 011 = 5 DRAM clocks 100 - 111 = Reserved Intel® 82925X/82925XE MCH Datasheet 87
MCHBAR Registers
R
Intel
®
82925X/82925XE MCH Datasheet
87
Bit
Access &
Default
Description
6:4
R/W
010b
DRAM RAS to CAS Delay (t
RCD
).
This bit controls the number of clocks inserted
between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = Reserved
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
3
Reserved
2:0
R/W
010b
DRAM RAS Precharge (t
RP
).
This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = Reserved
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved