Intel 925 Data Sheet - Page 88
C0DRC0-Channel A DRAM Controller Mode 0, MMIO Range, MCHBAR, Address Offset, Default Value, Access
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MCHBAR Registers R 5.1.10 C0DRC0-Channel A DRAM Controller Mode 0 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 120h 00000000h R/W 32 bits Bit 31:30 29 28:11 10:8 7 Access & Default Description R/W 0b R/W 000b RO 0b Reserved Initialization Complete (IC): This bit is used for communication of software state between the memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. Reserved Refresh Mode Select (RMS): This field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 000 = Refresh disabled 001 = Refresh enabled. Refresh interval 15.6 µsec 010 = Refresh enabled. Refresh interval 7.8 µsec 011 = Refresh enabled. Refresh interval 3.9 µsec 100 = Refresh enabled. Refresh interval 1.95 µsec 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved Reserved 88 Intel® 82925X/82925XE MCH Datasheet