Intel 925 Specification Update

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Manual

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  • Intel 925 | Specification Update - Page 1
    Intel® Pentium® D Processor 900Δ Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Δ Specification Update - On 65 nm Process in the 775-land LGA Package supporting Intel® 64 Architecture and Intel® Virtualization Technology± May 2008 Document Number: 310307-018
  • Intel 925 | Specification Update - Page 2
    units of this processor support Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information. Intel, Pentium, Celeron, Intel Core, Xeon and the Intel logo are trademarks
  • Intel 925 | Specification Update - Page 3
    Contents Contents ...3 Revision History ...4 Preface ...5 Summary Tables of Changes 7 General Information...13 Identification Information ...14 Errata ...16 Specification Changes ...32 Specification Clarifications 33 Documentation Changes ...34 Specification Update 3
  • Intel 925 | Specification Update - Page 4
    915 -012 -013 -014 -015 -016 -017 -018 • Added Erratum AA42 • Added Intel Pentium D processor 925 • Added D0-step • Added Intel Pentium D processor 935 • Updated names of Software Developers Manuals • Updated Summary table of changes • Added Erratum AA43 • Added AA44 • Added AA45 § Date December
  • Intel 925 | Specification Update - Page 5
    /products/ processor/manuals/index.htm http://www.intel.com/products/ processor/manuals/index.htm http://www.intel.com/products/ processor/manuals/index.htm http://www.intel.com/products/ processor/manuals/index.htm http://www.intel.com/products/ processor/manuals/index.htm Specification Update 5
  • Intel 925 | Specification Update - Page 6
    . Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number QDF Number is a several digit code that
  • Intel 925 | Specification Update - Page 7
    or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of apply to listed stepping. Status Doc: PlanFix: Fixed: NoFix: Document change or update that will be implemented. This erratum may be fixed in a future stepping
  • Intel 925 | Specification Update - Page 8
    updates: A = Dual-Core Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.80 GHz E = Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D F = processor I = Dual-Core Intel® Xeon® processor
  • Intel 925 | Specification Update - Page 9
    Intel® Core™2 Quad processor Q6000 sequence Dual-Core Intel® Xeon® processor 7100 series Intel® Celeron® processor 400 sequence Intel® Pentium® dual-core processor Quad-Core Intel® Xeon® processor 3200 series Dual-Core Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor
  • Intel 925 | Specification Update - Page 10
    ) May Update Memory outside the BTS/PEBS Buffer AA11 X X X No Fix Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Memory Record Access to an Unsupported Address Range in Uniprocessor (UP) AA14 X X X No Fix or Dual-processor (DP) Systems Supporting Intel
  • Intel 925 | Specification Update - Page 11
    X Plan VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Fix Ignores Reserved Bit settings in VM-exit Control Field AA33 X X X Memory Access May be Issued During Execution of the WRMSR Instruction Under Certain Conditions AA44 X Plan Combining Some Processors With Intel 945® Chipsets
  • Intel 925 | Specification Update - Page 12
    Summary Tables of Changes Number Plan SPECIFICATION CLARIFICATIONS There are no Specification Clarification in this Specification Update revision Number Plan DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § 12 Specification Update
  • Intel 925 | Specification Update - Page 13
    General Information General Information Figure 1. Intel® Pentium® D Processor 900 Sequence (Package Top Markings) Figure 2. Intel® Pentium® Processor Extreme Edition 965 (Package Top Markings) § Specification Update 13
  • Intel 925 | Specification Update - Page 14
    Intel Processor Identification and the CPUID Instruction Application Note (AP-485). Table 1. Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Identification Information S-Spec Core 5, 6 915 2.80GHz/800MHz 775-Land LGA 1, 3 14 Specification Update
  • Intel 925 | Specification Update - Page 15
    and Intel® Pentium® Processor Extreme Edition 955, 965 Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus Package Notes SL9D9 C1 SL9QB C1 SL95X C1 SL95W C1 SL95V C1 SL9AP C1 SL9AN C1 SL9KB D0 SL9KA D0
  • Intel 925 | Specification Update - Page 16
    in any commercially available operating system or application. The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being unsupported in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3, section 10.12.4, Programming the PAT. However, if
  • Intel 925 | Specification Update - Page 17
    Reserved Bit Checking When in PAE Paging Problem: The MOV CR3 instruction should perform reserved bit checking on the in a processor with HyperThreading enabled may cause a speculative page-table walk to be prematurely terminated, resulting in a processor hang and Changes. Specification Update 17
  • Intel 925 | Specification Update - Page 18
    Addresses on Processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Problem: If an x87 data instruction has been Table Base Address May Not Match the Address Bit Width Supported by the Platform Problem: If the page table base address, included in the 18 Specification Update
  • Intel 925 | Specification Update - Page 19
    Update Memory outside the BTS/PEBS Buffer Problem: Intel® Architecture Software Developer's Manual, Volume 3. Status: For the steppings affected, see the Summary Tables of Changes. AA11. Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled Problem
  • Intel 925 | Specification Update - Page 20
    of Changes. AA13. Problem: A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported Incorrectly in the Branch Trace Store (BTS) Memory Record or in the Precise Event Based Sampling (PEBS) Memory Record On a processor supporting Intel® EM64T, • If an instruction fetch wraps around the
  • Intel 925 | Specification Update - Page 21
    Unexpected Memory Access Problem: In a system supporting Intel® Virtualization Technology and Intel® Extended Memory 64 Technology, if the "CR8-store exiting" bit in the processor-based VM-execution control field is set and the "use TPR shadow" bit is not set, a MOV from CR8 instruction executed
  • Intel 925 | Specification Update - Page 22
    Problem: Power Down Requests May not be Serviced if a Power Down Transition is Interrupted by an In-Target Probe Event in the Presence of a Specific Type of VM Exit In a system supporting Intel® Virtualization Technology, the processor may service delayed by one instruction. Workaround: None
  • Intel 925 | Specification Update - Page 23
    May Not Correctly Clear the Interruptibility State Bits Problem: When a pending FP exception is ready to Memory Accesses In a system supporting Intel® Virtualization Technology, the processor may incorrectly VM exit under the following conditions: 1. Interrupt-Window-Exiting VM-execution control
  • Intel 925 | Specification Update - Page 24
    Exceptions May not Update Last-Exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check (EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround: Any vector
  • Intel 925 | Specification Update - Page 25
    . AA28. Problem: The Execution of VMPTRLD or VMREAD May Cause an Unexpected Memory Access On processors supporting Intel® Virtualization Technology, executing a VMPTRLD or a VMREAD instruction outside of VMX For the steppings affected, see the Summary Tables of Changes. Specification Update 25
  • Intel 925 | Specification Update - Page 26
    errors when cache transactions are in-flight and RESET# is asserted: •Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153) •L2 Data Problem: VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field Processors supporting Intel®
  • Intel 925 | Specification Update - Page 27
    memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel Tables of Changes. Specification Update 27
  • Intel 925 | Specification Update - Page 28
    the Same Time Problem: When two enabled Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction IRET instruction is returning Table Problem: In IA-32e mode of the Intel EM64T processor, control transfers system hang. Intel has not observed
  • Intel 925 | Specification Update - Page 29
    /chipsets which do not block new transactions during RESET# assertions. Status: For the steppings affected, see the Summary Tables of Changes AA40. Problem: NMI-blocking Information Recorded in VMCS May be Incorrect after a #GP on an IRET Instruction In a system supporting Intel® Virtualization
  • Intel 925 | Specification Update - Page 30
    945® Chipsets Can Lead to Unpredictable System Behavior Problem: Some processors with 800 MHz Front Side Bus (FSB), when used in combination with a motherboard based on the Intel 945® chipset, may observe FSB bit errors which may result in unpredictable system behavior. 30 Specification Update
  • Intel 925 | Specification Update - Page 31
    processor core to core transactions as well as during read transactions driven by the Memory Controller Problem: If a VM exit occurs while the processor is in IA-32e mode and the "host address-space size" VM-exit control always set the "IA-32e guest" VM-entry control in the SMM VMCS to be the value
  • Intel 925 | Specification Update - Page 32
    to the following documents: • Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details. § 32 Specification Update
  • Intel 925 | Specification Update - Page 33
    900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 documentation. § Specification Update 33
  • Intel 925 | Specification Update - Page 34
    will be incorporated into a future version of the appropriate Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 documentation. Note: Documentation changes for Intel® 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted
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Intel
®
Pentium
®
D Processor 900
Δ
Sequence and Intel
®
Pentium
®
Processor Extreme Edition 955,
965
Δ
Specification Update
- On 65 nm Process in the 775-land LGA Package
supporting Intel® 64 Architecture and Intel
®
Virtualization
Technology
±
May 2008
Document Number:
310307-018